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M32C/80 Group
SINGLE-CHIP 16/32-BIT CMOS MICROCOMPUTER
REJ03B0038-0110 Rev.1.10 Nov. 01, 2005
1. Overview
The M32C/80 Group microcomputer is a single-chip control unit that utilizes high-performance silicon gate CMOS technology with the M32C/80 series CPU core. The M32C/80 Group is available in 100-pin plastic molded LQFP/QFP package. With a 16-Mbyte address space, this microcomputer combines advanced instruction manipulation capabilities to process complex instructions by less bytes and execute instructions at higher speed. It incorporates a multiplier and DMAC adequate for office automation, communication devices and industrial equipments and other high-speed processing applications.
The M32C/80 Group is ROMless device. Use the M32C/80 Group in microprocessor mode after reset.
1.1 Applications
Audio, cameras, office equipment, communications equipment, portable equipment, etc.
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M32C/80 Group
1. Overview
1.2 Performance Overview
Table 1.1 lists performance overview of the M32C/80 Group. Table 1.1 M32C/80 Group Performance
CPU Item Basic Instructions Minimum Instruction Execution Time Performance 108 instructions 31.3 ns ( f(BCLK)=32 MHz, VCC1=4.2 to 5.5 V ) 41.7 ns ( f(BCLK)=24 MHz, VCC1=3.0 to 5.5 V ) Single-chip mode, Memory expansion mode, Microprocessor mode 16 Mbytes See Table 1.2 47 I/O pins (when using 16-bit bus) and 1 input pin Timer A: 16 bits x 5 channels, Timer B: 16 bits x 6 channels Three-phase motor control circuit 2 channels 5 channels Clock synchronous serial I/O, Clock asynchronous serial I/O, IEBus(1), I2C Bus(2) 10-bit A/D converter: 1 circuit, 10 channels 8 bits x 2 channels 4 channels Can be activated by all peripheral function interrupt sources Immediate transfer, operation and chain transfer function CRC-CCITT 16 bits x 16 bits 15 bits x 1 channel (with prescaler) 34 internal sources and 8 external sources, 5 software sources Interrupt priority level: 7 4 circuits Main Clock oscillation circuit (*), Sub clock oscillation circuit (*), On-chip oscillator, PLL frequency synthesizer (*)Equipped with a built-in feedback resistor Main clock oscillation stop detect circuit VCC1=4.2 to 5.5 V, VCC2=3.0 to VCC1 (f(BCLK)=32 MHz) VCC1=3.0 to 5.5 V, VCC2=3.0 to VCC1 (f(BCLK)=24 MHz) 22 mA (VCC1=VCC2=5 V, f(BCLK)=32 MHz) 17 mA (VCC1=VCC2=3.3 V, f(BCLK)=24 MHz) 10 A (VCC1=VCC2=3.3 V, f(BCLK)=32 kHz, in wait mode) -20 to 85oC, -40 to 85oC(optional) 100-pin plastic molded LQFP/QFP
Operating Mode Memory Space Memory Capacity Peripheral I/O Port function Multifunction Timer Intelligent I/O Communication Function Serial I/O
A/D Converter D/A Converter DMAC DMAC II CRC Calculation Circuit X/Y Converter Watchdog Timer Interrupt Clock Generation Circuit
Oscillation Stop Detect Function Electrical Supply Voltage Characteristics Power Consumption
Operating AmbientTemperature Package NOTES:
1. IEBus is a trademark of NEC Electronics Corporation. 2. I2C bus is a trademark of Koninklijke Philips Electronics N. V. All options are on a request basis.
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M32C/80 Group
1. Overview
1.3 Block Diagram
Figure 1.1 shows a block diagram of the M32C/80 Group microcomputer.
8
(1)
8
(2)
8
(1)
8
(1)
8
(1)
8
(1)
Port P0
Port P1
Port P2
Port P3
Port P4
Port P5

Port P6
Peripheral Functions
A/D Converter 1 circuit Standard: 8 inputs Maximum: 10 inputs
Timer (16 bits) Timer A: 5 channels Timer B: 6 channels UART/ Clock Synchronous Serial I/O 5 channels
Clock Generating Circuit XIN - XOUT XCIN - XCOUT On-chip Oscillator PLL Frequency Synthesizer DMAC DMACII
8
Port P7 Port P8
8
Three-phase Motor Control Circuit
X/Y converter 16 bits X 16 bits
CRC Calcilation Circuit (CCITT) X16+X12+X5+1
7

Watchdog Timer (15 bits) R0H R1H D/A Converter 8 bits X 2 channels A0 Intelligent I/O Communication Function 2 channels A1 FB SB R2 R3
M32C/80 series CPU core
R0L R1L FLG INTB ISP USP PC SVF SVP VCT
Memory
P85
RAM
Port P9 Port P10
8
Multiplier
8
NOTES: 1. Ports P0 to P5 function as bus control pins when using memory expansion mode or microprocessor mode. 2. Port P1 functions as I/O port when the microcomputer is placed in memory expansion mode or microprocessor mode and all external data buses are selected as 8-bit buses.
Figure 1.1 M32C/80 Group Block Diagram
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M32C/80 Group
1. Overview
1.4 Product Information
Table 1.2 lists the product information. Figure 1.2 shows the product numbering system. Table 1.2 M32C/80 Group
Type Number M30800SAGP M30800SAFP M30800SAGP-BL M30800SAFP-BL Package Type PLQP0100KB-A (100P6Q-A) ROMless PRQP0100JB-A (100P6S-A) PLQP0100KB-A (100P6Q-A) PRQP0100JB-A (100P6S-A) ROM Capacity
As of November, 2005
RAM Capacity Remarks
-
8K ROMless with on-chip boot loader
M30800 S A GP -BL
On-chip boot loader Package type: FP = Package PRQP0100JB-A (100P6S-A) GP = Package PLQP0100KB-A (100P6Q-A) Memory type: S = ROMless version RAM capacity, pin count, etc M32C/80 Group M16C Family
Figure 1.2 Product Numbering System
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M32C/80 Group
STxD4 / SCL4 / RxD4 / ADTRG / P97 KI0 / AN4 / P104 KI1 / AN5 / P105 KI2 / AN6 / P106 KI3 / AN7 / P107 AN1 / P101 D0 / P00 D1 / P01 D2 / P02 D3 / P03 D4 / P04 D5 / P05 D6 / P06 D7 / P07 AN2 / P102 AN3 / P103 AN0 / P100 AVss 88 81 97 96 95 94 93 92 91 90 89 87 86 85 84 83 82 VREF 98 AVcc 99
1.5 Pin Assignment
NOTE: 100
SRxD4 / SDA4 / TxD4 / ANEX1 / P96 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 74 75 76 77 78 P12 / D10 P13 / D11 P14 / D12 P15 / D13 / INT3 P16 / D14 / INT4 P17 / D15 / INT5 P20 / A0 ( / D0 ) P21 / A1 ( / D1 ) P22 / A2 ( / D2 ) P23 / A3 ( / D3 ) P24 / A4 ( / D4 ) P25 / A5 ( / D5 ) P26 / A6 ( / D6 ) P27 / A7 ( / D7 ) Vss P30 / A8 ( / D8 ) Vcc2 P31 / A9 ( / D9 ) P32 / A10 ( / D10 ) P33 / A11 ( / D11 ) P34 / A12 ( / D12 ) P35 / A13 ( / D13 ) P36 / A14 ( / D14 ) P37 / A15 ( / D15 ) P40 / A16 P41 / A17 P42 / A18 P43 / A19 79 P11 / D9 80 CLK4 / ANEX0 / P95 SS4 / RTS4 / CTS4 / TB4IN / DA1 / P94 SS3 / RTS3 / CTS3 / TB3IN / DA0 / P93 SRxD3 / SDA3 / TxD3 / TB2IN / P92 STxD3 / SCL3 / RxD3 / TB1IN / P91 CLK3 / TB0IN / P90 BYTE CNVss XCIN / P87 XCOUT / P86 RESET XOUT Vss XIN Vcc1 NMI / P85 INT2 / P84 INT1 / P83 INT0 / P82 U / TA4IN / P81 ISRxD0 / U / TA4OUT / P80 ISCLK0 / TA3IN / P77 ISTxD0 / TA3OUT / P76 ISRxD1 / W / TA2IN / P75 ISCLK1 / W / TA2OUT / P74 ISTxD1 / SS2 / RTS2 / CTS2 / V / TA1IN / P73 CLK2 / V / TA1OUT / P72 STxD2 / SCL2 / RxD2 / TA0IN / TB5IN / P71 SRxD2 / SDA2 / TxD2 / TA0OUT / P70 P10 / D8
Figure 1.3 Pin Assignment
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Figures 1.3 and 1.4 show pin assignments (top view).
1. P70 and P71 are ports for the N-channel open drain output.
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M32C/80 GROUP

33 P65 / CLK1 44 31 32 34 P64 / CTS1 / RTS1 / SS1 35 36 37 P61 / CLK0 38 P60 / CTS0 / RTS0 / SS0 39 P57 / RDY 40 P56 / ALE 41 P55 / HOLD 42 P54 / HLDA / ALE 43 45 P52 / RD P51 / WRH / BHE
46 P50 / WRL / WR
47 P47 / CS0 / A23
48 P46 / CS1 / A22
49 P45 / CS2 / A21
50 P44 / CS3 / A20
PRQP0100JB-A (100P6S-A)
P66 / RxD1 / SCL1 / STxD1
P62 / RxD0 / SCL0 / STxD0
P53 / CLKOUT / BCLK / ALE
P67 / TxD1 / SDA1 / SRxD1
P63 / TxD0 / SDA0 / SRxD0
1. Overview
M32C/80 Group
1. Overview
P32 / A10 ( / D10 )
P34 / A12 ( / D12 )
P35 / A13 ( / D13 )
P36 / A14 ( / D14 )
P37 / A15 ( / D15 ) 53
P33 / A11 ( / D11 )
P15 / D13 / INT3
P16 / D14 / INT4
P17 / D15 / INT5
P20 / A0 ( / D0 )
P14 / D12
P13 / D11
P31 / A9 ( / D9 )
P21 / A1 ( / D1 )
P22 / A2 ( / D2 )
P24 / A4 ( / D4 )
P25 / A5 ( / D5 )
P23 / A3 ( / D3 )
P26 / A6 ( / D6 )
P27 / A7 ( / D7 )
P30 / A8 ( / D8 )
P40 / A16 52
75
74
73
72
71
70
69
68
67
65
64
63
62
61
60
Vcc2
Vss
59
58
57
56
54
51
50
66
D10 / P12 D9 / P11 D8 / P10 D7 / P07 D6 / P06 D5 / P05 D4 / P04 D3 / P03 D2 / P02 D1 / P01 D0 / P00 KI3 / AN7 / P107 KI2 / AN6 / P106 KI1 / AN5 / P105 KI0 / AN4 / P104 AN3 / P103 AN2 / P102 AN1 / P101 AVss AN0 / P100 VREF AVcc STxD4 / SCL4 / RxD4 / ADTRG / P97 SRxD4 / SDA4 / TxD4 / ANEX1 / P96 CLK4 / ANEX0 / P95
55
P41 / A17
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
P42 / A18 P43 / A19 P44 / CS3 / A20 P45 / CS2 / A21 P46 / CS1 / A22 P47 / CS0 / A23 P50 / WRL / WR P51 / WRH / BHE P52 / RD P53 / CLKOUT / BCLK / ALE P54 / HLDA / ALE P55 / HOLD P56 / ALE P57 / RDY P60 / CTS0 / RTS0 / SS0 P61 / CLK0 P62 / RxD0 / SCL0 / STxD0 P63 / TxD0 / SDA0 / SRxD0 P64 / CTS1 / RTS1 / SS1 P65 / CLK1 P66 / RxD1 / SCL1 / STxD1 P67 / TxD1 / SDA1 / SRxD1 P70 / TA0OUT / TxD2 / SDA2 / SRxD2 P71 / TA0IN / TB5IN / RxD2 / SCL2 / STxD2 P72 / TA1OUT / V / CLK2

49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26
M32C/80 GROUP

10 12 13 14 15 16 17 18 19 20 21 22 23 ISRxD1 / W / TA2IN / P75 24 ISCLK1 / W / TA2OUT / P74 25 ISTxD1 / SS2 / RTS2 / CTS2 / V / TA1IN / P73 11 XOUT 1 2 3 4 5 6 7 8 9
BYTE
RESET
Vss
SS4 / RTS4 / CTS4 / TB4IN / DA1 / P94
SS3 / RTS3 / CTS3 / TB3IN / DA0 / P93
SRxD3 / SDA3 / TxD3 / TB2IN / P92
STxD3 / SCL3 / RxD3 / TB1IN / P91
CLK3 / TB0IN / P90
XCIN / P87
XCOUT / P86
XIN
NMI / P85
INT2 / P84
INT1 / P83
INT0 / P82
U / TA4IN / P81
ISRxD0 / U / TA4OUT / P80
ISCLK0 / TA3IN / P77
NOTE: 1. P70 and P71 are ports for the N-channel open drain output.
ISTxD0 / TA3OUT / P76
CNVss
Vcc1
PLQP0100KB-A (100P6Q-A)
Figure 1.4 Pin Assignment
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M32C/80 Group
1. Overview
Table 1.3 Pin Characteristics
Package Pin No
FP GP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 99 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
Control pins
Port P96 P95 P94 P93 P92 P91 P90
Interrupt pins
Timer pins
UART pins TxD4/SDA4/SRxD4 CLK4 CTS4/RTS4/SS4 CTS3/RTS3/SS3 TxD3/SDA3/SRxD3 RxD3/SCL3/STxD3 CLK3
Analog pins ANEX1 ANEX0 DA1 DA0
Bus control pins
Intelligent I/O pins
TB4IN TB3IN TB2IN TB1IN TB0IN
BYTE CNVSS XCIN XCOUT RESET XOUT VSS XIN VCC1
P87 P86
P85 P84 P83 P82 P81 P80 P77 P76 P75 P74 P73 P72 P71 P70 P67 P66 P65 P64 P63 P62 P61 P60 P57 P56 P55 P54 P53 P52 P51 P50 P47 P46 P45 P44
NMI INT2 INT1 INT0 TA4IN/U TA4OUT/U TA3IN TA3OUT TA2IN/W TA2OUT/W TA1IN/V TA1OUT/V TB5IN/TA0IN TA0OUT ISRxD0 ISCLK0 ISTxD0 ISRxD1 ISCLK1 ISTxD1
CTS2/RTS2/SS2 CLK2 RxD2/SCL2/STxD2 TxD2/SDA2/SRxD2 TxD1/SDA1/SRxD1 RxD1/SCL1/STxD1 CLK1 CTS1/RTS1/SS1 TxD0/SDA0/SRxD0 RxD0/SCL0/STxD0 CLK0 CTS0/RTS0/SS0 RDY ALE HOLD HLDA/ALE CLKOUT/BCLK/ALE RD WRH/BHE WRL/WR CS0/A23 CS1/A22 CS2/A21 CS3/A20
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M32C/80 Group
1. Overview
Table 1.3 Pin Characteristics (Continued)
Package pin No FP GP 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 AVSS P100 AVCC P97 RxD4/SCL4/STxD4 ADTRG AN0 VREF VCC2 P30 VSS P27 P26 P25 P24 P23 P22 P21 P20 P17 P16 P15 P14 P13 P12 P11 P10 P07 P06 P05 P04 P03 P02 P01 P00 P107 P106 P105 P104 P103 P102 P101 KI3 KI2 KI1 KI0 AN7 AN6 AN5 AN4 AN3 AN2 AN1 INT5 INT4 INT3 A7(/D7) A6(/D6) A5(/D5) A4(/D4) A3(/D3) A2(/D2) A1(/D1) A0(/D0) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 A8(/D8) Control pins Port P43 P42 P41 P40 P37 P36 P35 P34 P33 P32 P31 Interrupt pins Timer pins UART pins Analog pins A19 A18 A17 A16 A15(/D15) A14(/D14) A13(/D13) A12(/D12) A11(/D11) A10(/D10) A9(/D9) Bus control pins Intelligent I/O pins
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M32C/80 Group
1. Overview
1.6 Pin Description
Table 1.4 Pin Description
Signal name Power supply Analog power supply input Reset input CNVSS External data bus width select input Bus control pins D0 to D7 D8 to D15 A0 to A22
______
Pin name I/O type VCC1, VCC2 VSS AVCC AVSS ____________ RESET CNVSS BYTE I I I I I
Supply voltage VCC1 VCC1 VCC1 VCC1
Description Apply 3.0 to 5.5 V to both VCC1 and VCC2 pins. Apply 0 V to the VSS pin. VCC1 VCC2(1) Supplies power for the A/D converter. Connect the AVCC pin to VCC1 and the AVSS pin to VSS The microcomputer is in a reset state when "L" is applied to the
____________
RESET pin Connect this pin to VCC1 Switches the data bus in external memory space 3. The data bus is 16 bits long when the this pin is held "L" and 8 bits long when the this pin is held "H". Set it to either one. Inputs and outputs data (D0 to D7) while accessing an external memory space with separate bus Inputs and outputs data (D8 to D15) while accessing an external memory space with 16-bit separate bus Outputs address bits (A0 to A22) Outputs inversed address bit A23 Inputs and outputs data (D0 to D7) and outputs 8 low-order address bits (A0 to A7) by time-sharing while accessing an external memory space with multiplexed bus
I/O I/O O O I/O
VCC2 VCC2 VCC2 VCC2 VCC2
A23 A0/D0 to A7/D7 A8/D8 to A15/D15
______ ______
I/O
VCC2
Inputs and outputs data (D8 to D15) and outputs 8 middle-order address bits (A8 to A15) by time-sharing while accessing an external memory space with multiplexed bus ______ ______ Output CS0 to CS3 that are chip-select signals specifying an external space
_______ ________ ______ ________ _____ _______ ________
CS0 to CS3
________ ______
O O
VCC2 VCC2
WRL/WR _________ ________ WRH/BHE
_____
Outputs WRL, WRH, (WR, BHE) and RD signals. WRL and WRH ______ _______ can be switched with WR and BHE by program
________ _________ _____
RD
WRL, WRH and RD are selected: If external data bus is 16 bits wide, data is writtenn to an even
_______
address when WRL is held "L". ________ Data is written to an odd address when WRH is held "L".
_____
Data is read when RD is held "L". ______ ________ _____ WR, BHE and RD are selected
______
Data is written to external memory space when WR is held "L". _____ Data is read when RD is held "L".
________
An odd address is accessed when BHE is held "L". ______ ________ _____ Select WR, BHE and RD for an external 8-bit data bus ALE __________ HOLD
__________
O I O I
VCC2 VCC2 VCC2 VCC2
ALE is a signal latching address __________ The microcomputer is placed in a hold state while the HOLD pin is held "L" Outputs an "L" siganl while the microcomputer is placed in a hold state Bus is placed in a wait state while the RDY pin is held "L"
HLDA
________
RDY I: Input O: Output
I/O: Input and output
NOTE: 1. In this manual, hereafter, VCC refers to VCC1 unless otherwise noted.
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M32C/80 Group
1. Overview
Table 1.4 Pin Description (Continued)
Signal name Pin name I/O type I O I O O O I I I I/O I I O I O I/O I O I/O I/O I I I Supply voltage VCC1 VCC1 VCC1 VCC1 VCC2 VCC2 VCC1 VCC2 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 Description I/O pins for the main clock generation circuit. Connect a ceramic resonator or crystal oscillator between XIN and XOUT. To apply external clock, input the clock from XIN and leave XOUT open I/O pins for a sub clock oscillation circuit. Connect a crystal oscillator between XCIN and XCOUT. To apply external clock, input the clock from XCIN and leave XCOUT open Outputs BCLK signal Outputs clock having thesame frequency as fC, f8, or f32
______
Main clock input XIN Main clock output XOUT
Sub clock input XCIN Sub clock XCOUT output BCLK output Clock output ______ INT interrupt
_______
BCLK CLKOUT _______ _______ INT0 to INT2
_______ _______
Input pins for the INT interrupt
_______
input INT3 to INT5 _______ NMI interrupt input NMI
_____ _____
Key input interrupt KI0 to KI3 Timer A TA0OUT to TA4OUT TA0IN to Timer B TA4IN TB0IN to
Input pin for the NMI interrupt Input pins for the key input interrupt I/O pins for the timer A0 to A4 (TA0OUT is a pin for the N-channel open drain output.) Input pins for the timer A0 to A4 Input pins for the timer B0 to B5 output pins for the three-phase motor control timer Input pins for data transmission control Output pins for data reception control Inputs and outputs the transfer clock Inputs serial data Outputs serial data (TxD2 is a pin for the N-channel open drain output.) Inputs and outputs serial data (SDA2 is a pin for for the Nchannel open drain output.) Inputs and outputs the transfer clock (SCL2 is a pin for the Nchannel open drain output.) Outputs serial data when slave mode is selected (SDA2 is a pin for the N-channel open drain output.) Inputs serial data when slave mode is selected Input pins to control serial I/O special function
TB5IN __ __ Three-phase motor U, U, V, V,
__
control output Serial I/O
W, W _________ CTS0 to
_________
CTS4 _________ RTS0 to
_________
RTS4 CLK0 to CLK4 RxD0 to RxD4 TxD0 to I 2C mode TxD4 SDA0 to SDA4 SCL0 to Serial I/O SCL4 STxD0 to
special function STxD4 SRxD0 to SRxD4 ______ _______ SS0 to SS4 I: Input O: Output
I/O: Input and output
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M32C/80 Group
1. Overview
Table 1.5 Pin Description (Continued)
Signal name Reference voltage input A/D converter Pin name I/O type VREF AN0 to AN7 ___________ ADTRG ANEX0 ANEX1 DA0, DA1 I I I I/O I O I/O O I I/O Supply voltage VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC2 Description Applies reference voltage for the A/D converter and D/A converter Analog input pins for the A/D converter Input pin for an external A/D trigger Extended analog input pin for the A/D converter and output pin in external op-amp connection mode Extended analog input pin for the A/D converter Output pin for the D/A converter Inputs and outputs clock for the intelligent I/O communication fucntion Outputs data for the intelligent I/O communication fucntion Inputs data for the intelligent I/O communication fucntion I/O ports fro CMOS. Each port can be programmed for nput or output under the control of the direction register. An input port can be set, by program, for a pull-up resistor available or for no pull-up resistor available in 4-bit units
D/A converter
Intelligent I/O ISCLK0 communication ISCLK1 function ISTxD0 ISTxD1 ISRxD0 ISRxD1 I/O port P00 to P07(1) P10 to P17(2) P20 to P27(1) P30 to P37(1) P40 to P47(1) P50 to P57(1) P60 to P67 P70 to P77 P90 to P97 P100 to P107 P80 to P84, P86, P87 P85 O: Output
I/O
VCC1
I/O ports having equivalent functions to P0 (P70 and P71 are ports for the N-channel open drain output.)
I/O I
VCC1 VCC1
I/O ports having equivalent functions to P0
_______ _______
Shares a pin with NMI. NMI input state can be got by reading P85
I: Input NOTES:
I/O: Input and output
1. Ports P0 to P5 function as bus control pins when using memory expansion mode or microprocessor mode. They cannot be used as I/O ports. 2. Port P1 functions as I/O port when the microcomputer is placed in memory expansion mode or microprocessor mode and all external data buses are selected as 8-bit buses.
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M32C/80 Group
2. Central Processing Unit (CPU)
2. Central Processing Unit (CPU)
Figure 2.1 shows the CPU registers. The register bank is comprised of 8 registers (R0, R1, R2, R3, A0, A1, SB and FB) out of 28 CPU registers. Two sets of register banks are provided.
b31
b15
b0
General Registers
R2 R3
R0H R1H R2
R0L R1L Data Register(1)
b23
R3 A0 A1 SB FB USP ISP INTB PC FLG Address Register(1) Static Base Register(1) Frame Base Register(1) User Stack Pointer Interrupt Stack Pointer Interrupt Table Register Program Counter Flag Register
b0
b15
b8 b7
IPL
U I OBSZDC
Carry Flag Debug Flag Zero Flag Sign Flag Register Bank Select Flag Overflow Flag Interrupt Enable Flag Stack Pointer Select Flag Reserved Space Processor Interrupt Priority Level Reserved Space
b15 b0
High-speed Interrupt Registers
b23
SVF SVP VCT
b7 b0
Flag Save Register PC Save Register Vector Register
DMAC-associated Registers
b15
DMD0 DMD1 DCT0 DCT1 DRC0
b23
DMA Mode Register
DMA Transfer Count Register
DRC1 DMA0 DMA1 DRA0 DRA1 DSA0 DSA1
DMA Transfer Count Reload Register
DMA Memory Address Register
DMA Memory Address Reload Register
DMA SFR Address Register
NOTE: 1. The register bank is comprised of these registers. Two sets of register banks are provided.
Figure 2.1 CPU Register
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M32C/80 Group
2. Central Processing Unit (CPU)
2.1 General Registers 2.1.1 Data Registers (R0, R1, R2 and R3)
R0, R1, R2 and R3 are 16-bit registers for transfer, arithmetic and logic operations. R0 and R1 can be split into high-order bits (R0H) and low-order bits (R0L) to be used separately as 8-bit data registers. R0 can be combined with R2 to be used as a 32-bit data register (R2R0). The same applies to R1 and R3.
2.1.2 Address Registers (A0 and A1)
A0 and A1 are 24-bit registers for A0-/A1-indirect addressing, A0-/A1-relative addressing, transfer, arithmetic and logic operations.
2.1.3 Static Base Register (SB)
SB is a 24-bit register for SB-relative addressing.
2.1.4 Frame Base Register (FB)
FB is a 24-bit register for FB-relative addressing.
2.1.5 Program Counter (PC)
PC, 24 bits wide, indicates the address of an instruction to be executed.
2.1.6 Interrupt Table Register (INTB)
INTB is a 24-bit register indicating the starting address of an relocatable interrupt vector table.
2.1.7 User Stack Pointer (USP), Interrupt Stack Pointer (ISP)
The stack pointers (SP), USP and ISP, are 24 bits wide each. The U flag is used to switch between USP and ISP. Refer to 2.1.8 Flag Register (FLG) for details on the U flag. Set USP and ISP to even addresses to execute an interrupt sequence efficiently.
2.1.8 Flag Register (FLG)
FLG is a 16-bit register indicating a CPU state. 2.1.8.1 Carry Flag (C) The C flag indicates whether carry or borrow has occurred after executing an instruction. 2.1.8.2 Debug Flag (D) The D flag is for debug only. Set to "0". 2.1.8.3 Zero Flag (Z) The Z flag is set to "1" when the value of zero is obtained from an arithmetic operation; otherwise "0". 2.1.8.4 Sign Flag (S) The S flag is set to "1" when a negative value is obtained from an arithmetic operation; otherwise "0".
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2. Central Processing Unit (CPU)
2.1.8.5 Register Bank Select Flag (B) The register bank 0 is selected when the B flag is set to "0". The register bank 1 is selected when this flag is set to "1". 2.1.8.6 Overflow Flag (O) The O flag is set to "1" when the result of an arithmetic operation overflows; otherwise "0". 2.1.8.7 Interrupt Enable Flag (I) The I flag enables a maskable interrupt. Interrupt is disabled when the I flag is set to "0" and enabled when the I flag is set to "1". The I flag is set to "0" when an interrupt is acknowledged. 2.1.8.8 Stack Pointer Select Flag (U) ISP is selected when the U flag is set to "0". USP is selected when this flag is set to "1". The U flag is set to "0" when a hardware interrupt is acknowledged or the INT instruction of software interrupt numbers 0 to 31 is executed. 2.1.8.9 Processor Interrupt Priority Level (IPL) IPL, 3 bits wide, assigns processor interrupt priority levels from level 0 to level 7. If a requested interrupt has greater priority than IPL, the interrupt is enabled. 2.1.8.10 Reserved Space When writing to a reserved space, set to "0". When reading, its content is indeterminate.
2.2 High-Speed Interrupt Registers
Registers associated with the high-speed interrupt are as follows: - Flag save register (SVF) - PC save register (SVP) - Vector register (VCT)
2.3 DMAC-Associated Registers
Registers associated with DMAC are as follows: - DMA mode register (DMD0, DMD1) - DMA transfer count register (DCT0, DCT1) - DMA transfer count reload register (DRC0, DRC1) - DMA memory address register (DMA0, DMA1) - DMA SFR address register (DSA0, DSA1) - DMA memory address reload register (DRA0, DRA1)
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3. Memory
3. Memory
Figure 3.1 shows a memory map of the M32C/80 Group. The M32C/80 Group provides 16-Mbyte address space addressed from 00000016 to FFFFFF16. The fixed interrupt vectors are allocated from address FFFFDC16 to FFFFFF16. It stores the starting address of each interrupt routine. The internal RAM is allocated from address 00040016 to higher. For example, a 8-Kbyte internal RAM is allocated from address 00040016 to 0023FF16. Besides storing data, it becomes stacks when the subroutine is called or an interrupt is acknowledged. SFRs, consisting of control registers for peripheral functions such as I/O port, A/D converter, serial I/O, timers, is allocated from address 00000016 to 0003FF16. All blank spaces within SFRs are reserved and cannot be accessed by users. The special page vector table is addressed from FFFE0016 to FFFFDB16. It is used for the JMPS instruction and JSRS instruction. Refer to the Renesas publication M32C/80 Series Software Manual for details. In microprocessor mode, some spaces are reserved and cannot be accessed by users.
00000016 SFRs 00040016 0023FF16 01000016 Internal RAM Reserved Space FFFE0016 Special Page Vector Table FFFFDC16 Undefined Instruction Overflow BRK Instruction Address Match Watchdog Timer(1) NMI Reset
External Space
FFFFFF16
FFFFFF16
NOTE: 1. Watchdog timer interrupt and oscillation stop detection interrupt share vectors.
Figure 3.1 Memory Map
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4. Special Function Registers (SFRs)
4. Special Function Registers (SFRs)
Address 000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 001016 001116 001216 001316 001416 001516 001616 001716 001816 001916 001A16 001B16 001C16 001D16 001E16 001F16 002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A16 002B16 002C16 002D16 002E16 002F16 Register Symbol Value after RESET
Processor Mode Register(1) Processor Mode Register 1 System Clock Control Register 0 System Clock Control Register 1 Address Match Interrupt Enable Register Protect Register External Data Bus Width Control Register Main Clock Division Register Oscillation Stop Detection Register Watchdog Timer Start Register Watchdog Timer Control Register Address Match Interrupt Register 0 Processor Mode Register 2 Address Match Interrupt Register 1
PM0 PM1 CM0 CM1 AIER PRCR DS MCD CM2 WDTS WDC RMAD0 PM2 RMAD1
0000 00112(CNVss pin ="H") 0016 0000 10002 0010 00002 0016 XXXX 00002 XXXX 10002(BYTE pin ="L") XXXX 00002(BYTE pin ="H") XXX0 10002 0016 XX16 000X XXXX2 00000016 0016 00000016
Address Match Interrupt Register 2
RMAD2
00000016
Address Match Interrupt Register 3
RMAD3
00000016
PLL Control Register 0 PLL Control Register 1 Address Match Interrupt Register 4
PLC0 PLC1 RMAD4
0001 X0102 000X 00002 00000016
Address Match Interrupt Register 5
RMAD5
00000016
X: Indeterminate Blank spaces are reserved. No access is allowed. NOTE: 1. The PM01 and PM00 bits in the PM0 register maintain values set before reset, even after software reset or watchdog timer reset has been performed.
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4. Special Function Registers (SFRs)
Address 003016 003116 003216 003316 003416 003516 003616 003716 003816 003916 003A16 003B16 003C16 003D16 003E16 003F16 004016 004116 004216 004316 004416 004516 004616 004716 004816 004916 004A16 004B16 004C16 004D16 004E16 004F16 005016 005116 005216 005316 005416 005516 005616 005716 005816 005916 005A16 005B16 005C16 005D16 005E16 005F16
Register
Symbol
Value after RESET
Address Match Interrupt Register 6
RMAD6
00000016
Address Match Interrupt Register 7
RMAD7
00000016
External Space Wait Control Register 0 External Space Wait Control Register 1 External Space Wait Control Register 2 External Space Wait Control Register 3
EWCR0 EWCR1 EWCR2 EWCR3
X0X0 00112 X0X0 00112 X0X0 00112 X0X0 00112
X: Indeterminate Blank spaces are reserved. No access is allowed.
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4. Special Function Registers (SFRs)
Address 006016 006116 006216 006316 006416 006516 006616 006716 006816 006916 006A16 006B16 006C16 006D16 006E16 006F16 007016 007116 007216 007316 007416 007516 007616 007716 007816 007916 007A16 007B16 007C16 007D16 007E16 007F16 008016 008116 008216 008316 008416 008516 008616 008716 008816 008916 008A16 008B16 008C16 008D16 008E16 008F16
Register
Symbol
Value after RESET
DMA0 Interrupt Control Register Timer B5 Interrupt Control Register DMA2 Interrupt Control Register UART2 Receive /ACK Interrupt Control Register Timer A0 Interrupt Control Register UART3 Receive /ACK Interrupt Control Register Timer A2 Interrupt Control Register UART4 Receive /ACK Interrupt Control Register Timer A4 Interrupt Control Register UART0/UART3 Bus Conflict Detect Interrupt Control Register UART0 Receive/ACK Interrupt Control Register A/D0 Conversion Interrupt Control Register UART1 Receive/ACK Interrupt Control Register Intelligent I/O Interrupt Control Register 0 Timer B1 Interrupt Control Register Intelligent I/O Interrupt Control Register 2 Timer B3 Interrupt Control Register Intelligent I/O Interrupt Control Register 4 INT5 Interrupt Control Register INT3 Interrupt Control Register INT1 Interrupt Control Register
DM0IC TB5IC DM2IC S2RIC TA0IC S3RIC TA2IC S4RIC TA4IC BCN0IC/BCN3IC S0RIC AD0IC S1RIC IIO0IC TB1IC IIO2IC TB3IC IIO4IC INT5IC INT3IC INT1IC
XXXX X0002 XXXX X0002 XXXX X0002 XXXX X0002 XXXX X0002 XXXX X0002 XXXX X0002 XXXX X0002 XXXX X0002 XXXX X0002 XXXX X0002 XXXX X0002 XXXX X0002 XXXX X0002 XXXX X0002 XXXX X0002 XXXX X0002 XXXX X0002 XX00 X0002 XX00 X0002 XX00 X0002
DMA1 Interrupt Control Register UART2 Transmit /NACK Interrupt Control Register DMA3 Interrupt Control Register UART3 Transmit /NACK Interrupt Control Register Timer A1 Interrupt Control Register UART4 Transmit /NACK Interrupt Control Register Timer A3 Interrupt Control Register UART2 Bus Conflict Detect Interrupt Control Register
DM1IC S2TIC DM3IC S3TIC TA1IC S4TIC TA3IC BCN2IC
XXXX X0002 XXXX X0002 XXXX X0002 XXXX X0002 XXXX X0002 XXXX X0002 XXXX X0002 XXXX X0002
X: Indeterminate Blank spaces are reserved. No access is allowed.
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4. Special Function Registers (SFRs)
Address 009016 009116 009216 009316 009416 009516 009616 009716 009816 009916 009A16 009B16 009C16 009D16 009E16 009F16 00A016 00A116 00A216 00A316 00A416 00A516 00A616 00A716 00A816 00A916 00AA16 00AB16 00AC16 00AD16 00AE16 00AF16 00B016 00B116 00B216 00B316 00B416 00B516 00B616 00B716 00B816 00B916 00BA16 00BB16 00BC16 00BD16 00BE16 00BF16
Register UART0 Transmit /NACK Interrupt Control Register UART1/UART4 Bus Conflict Detect Interrupt Control Register UART1 Transmit/NACK Interrupt Control Register Key Input Interrupt Control Register Timer B0 Interrupt Control Register Intelligent I/O Interrupt Control Register 1 Timer B2 Interrupt Control Register Intelligent I/O Interrupt Control Register 3 Timer B4 Interrupt Control Register INT4 Interrupt Control Register INT2 Interrupt Control Register INT0 Interrupt Control Register Exit Priority Control Register Interrupt Request Register 0 Interrupt Request Register 1 Interrupt Request Register 2 Interrupt Request Register 3 Interrupt Request Register 4
Symbol S0TIC BCN1IC/BCN4IC S1TIC KUPIC TB0IC IIO1IC TB2IC IIO3IC TB4IC INT4IC INT2IC INT0IC RLVL IIO0IR IIO1IR IIO2IR IIO3IR IIO4IR
Value after RESET XXXX X0002 XXXX X0002 XXXX X0002 XXXX X0002 XXXX X0002 XXXX X0002 XXXX X0002 XXXX X0002 XXXX X0002 XX00 X0002 XX00 X0002 XX00 X0002 XXXX 00002 0000 000X2 0000 000X2 0000 000X2 0000 000X2 0000 000X2
Interrupt Enable Register 0 Interrupt Enable Register 1 Interrupt Enable Register 2 Interrupt Enable Register 3 Interrupt Enable Register 4
IIO0IE IIO1IE IIO2IE IIO3IE IIO4IE
0016 0016 0016 0016 0016
X: Indeterminate Blank spaces are reserved. No access is allowed.
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4. Special Function Registers (SFRs)
Address 00C016 00C116 00C216 00C316 00C416 00C516 00C616 00C716 00C816 00C916 00CA16 00CB16 00CC16 00CD16 00CE16 00CF16 00D016 00D116 00D216 00D316 00D416 00D516 00D616 00D716 00D816 00D916 00DA16 00DB16 00DC16 00DD16 00DE16 00DF16 00E016 00E116 00E216 00E316 00E416 00E516 00E616 00E716 00E816 00E916 00EA16 00EB16 00EC16 00ED16 00EE16 00EF16
Register
Symbol
Value after RESET
SI/O Receive Buffer Register 0 Transmit Buffer/Receive Data Register 0 Receive Input Register 0 SI/O Communication Mode Register 0 Transmit Output Register 0 SI/O Communication Control Register 0
G0RB G0TB/G0DR G0RI G0MR G0TO G0CR
XXXX XXXX2 XXX0 XXXX2 XX16 XX16 0016 XX16 0000 X0112
X: Indeterminate Blank spaces are reserved. No access is allowed.
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4. Special Function Registers (SFRs)
Address 00F016 00F116 00F216 00F316 00F416 00F516 00F616 00F716 00F816 00F916 00FA16 00FB16 00FC16 00FD16 00FE16 00FF16 010016 010116 010216 010316 010416 010516 010616 010716 010816 010916 010A16 010B16 010C16 010D16 010E16 010F16 011016 011116 011216 011316 011416 011516 011616 011716 011816 011916 011A16 011B16 011C16 011D16 011E16 011F16
Register Data Compare Register 00 Data Compare Register 01 Data Compare Register 02 Data Compare Register 03 Data Mask Register 00 Data Mask Register 01 Communication Clock Select Register
Symbol G0CMP0 G0CMP1 G0CMP2 G0CMP3 G0MSK0 G0MSK1 CCS
Value after RESET XX16 XX16 XX16 XX16 XX16 XX16 XXXX 00002 XX16
Receive CRC Code Register 0 Transmit CRC Code Register 0 SI/O Expansion Mode Register 0 SI/O Expansion Receive Control Register 0 SI/O Special Communication Interrupt Detect Register 0 SI/O Expansion Transmit Control Register 0
G0RCRC G0TCRC G0EMR G0ERC G0IRF G0ETC
XX16 0016 0016 0016 0016 0016 0000 0XXX2
X: Indeterminate Blank spaces are reserved. No access is allowed.
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4. Special Function Registers (SFRs)
Address 012016 012116 012216 012316 012416 012516 012616 012716 012816 012916 012A16 012B16 012C16 012D16 012E16 012F16 013016 013116 013216 013316 013416 013516 013616 013716 013816 013916 013A16 013B16 013C16 013D16 013E16 013F16 014016 014116 014216 014316 014416 014516 014616 014716 014816 014916 014A16 014B16 014C16 014D16 to 02AF16
Register
Symbol
Value after RESET
XXXX XXXX2 SI/O Receive Buffer Register 1 Transmit Buffer/Receive Data Register 1 Receive Input Register 1 SI/O Communication Mode Register 1 Transmit Output Register 1 SI/O Communication Control Register 1 Data Compare Register 10 Data Compare Register 11 Data Compare Register 12 Data Compare Register 13 Data Mask Register 10 Data Mask Register 11 G1RB G1TB/G1DR G1RI G1MR G1TO G1CR G1CMP0 G1CMP1 G1CMP2 G1CMP3 G1MSK0 G1MSK1 XXX0 XXXX2 XX16 XX16 0016 XX16 0000 X0112 XX16 XX16 XX16 XX16 XX16 XX16
XX16 Receive CRC Code Register 1 Transmit CRC Code Register 1 SI/O Expansion Mode Register 1 SI/O Expansion Receive Control Register 1 SI/O Special Communication Interrupt Detection Register 1 SI/O Expansion Transmit Control Register 1 G1RCRC G1TCRC G1EMR G1ERC G1IRF G1ETC XX16 0016 0016 0016 0016 0016 0000 0XXX2
X: Indeterminate Blank spaces are reserved. No access is allowed.
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4. Special Function Registers (SFRs)
Address 02B116 02B216 02B316 02B416 02B516 02B616 02B716 02B816 02B916 02BA16 02BB16 02BC16 02BD16 02BE16 02BF16 02C016 02C116 02C216 02C316 02C416 02C516 02C616 02C716 02C816 02C916 02CA16 02CB16 02CC16 02CD16 02CE16 02CF16 02D016 02D116 02D216 02D316 02D416 02D516 02D616 02D716 02D816 02D916 02DA16 02DB16 02DC16 02DD16 02DE16 02DF16 X0 Register Y0 Register X1 Register Y1 Register X2 Register Y2 Register X3 Register Y3 Register X4 Register Y4 Register X5 Register Y5 Register X6 Register Y6 Register X7 Register Y7 Register X8 Register Y8 Register X9 Register Y9 Register X10 Register Y10 Register X11 Register Y11 Register X12 Register Y12 Register X13 Register Y13 Register X14 Register Y14 Register X15 Register Y15 Register
Register
Symbol
Value after RESET
XX16 X0R,Y0R X1R,Y1R X2R,Y2R X3R,Y3R X4R,Y4R X5R,Y5R X6R,Y6R X7R,Y7R X8R,Y8R X9R,Y9R X10R,Y10R X11R,Y11R X12R,Y12R X13R,Y13R X14R,Y14R X15R,Y15R XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16
X: Indeterminate Blank spaces are reserved. No access is allowed.
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4. Special Function Registers (SFRs)
Address 02E016 02E116 02E216 02E316 02E416 02E516 02E616 02E716 02E816 02E916 02EA16
Register X/Y Control Register
Symbol XYC
Value after RESET XXXX XX002
UART1 Special Mode Register 4 UART1 Special Mode Register 3 UART1 Special Mode Register 2 UART1 Special Mode Register UART1 Transmit/Receive Mode Register UART1 Bit Rate Register
U1SMR4 U1SMR3 U1SMR2 U1SMR U1MR U1BRG U1TB U1C0 U1C1 U1RB
0016 0016 0016 0016 0016 XX16 XX16 XX16 0000 10002 0000 00102 XX16 XX16
UART1 Transmit Buffer Register 02EB16 02EC16 UART1 Transmit/Receive Control Register 0 02ED16 UART1 Transmit/Receive Control Register 1 02EE16 UART1 Receive Buffer Register 02EF16 02F016 02F116 02F216 02F316 02F416 UART4 Special Mode Register 4 02F516 UART4 Special Mode Register 3 02F616 UART4 Special Mode Register 2 02F716 UART4 Special Mode Register 02F816 UART4 Transmit/Receive Mode Register 02F916 UART4 Bit Rate Register 02FA16 UART4 Transmit Buffer Register 02FB16 02FC16 UART4 Transmit/Receive Control Register 0 02FD16 UART4 Transmit/Receive Control Register 1 02FE16 UART4 Receive Buffer Register 02FF16 030016 Timer B3, B4, B5 Count Start Flag 030116 030216 Timer A1-1 Register 030316 030416 Timer A2-1 Register 030516 030616 Timer A4-1 Register 030716 030816 Three-Phase PWM Control Register 0 030916 Three-Phase PWM Control Register 1 030A16 Three-Phase Output Buffer Register 0 030B16 Three-Phase Output Buffer Register 1 030C16 Dead Time Timer 030D16 Timer B2 Interrupt Generation Frequency Set Counter 030E16 030F16
U4SMR4 U4SMR3 U4SMR2 U4SMR U4MR U4BRG U4TB U4C0 U4C1 U4RB TBSR
0016 0016 0016 0016 0016 XX16 XX16 XX16 0000 10002 0000 00102 XX16 XX16 000X XXXX2 XX16
TA11 TA21 TA41 INVC0 INVC1 IDB0 IDB1 DTT ICTB2
XX16 XX16 XX16 XX16 XX16 0016 0016 XX11 11112 XX11 11112 XX16 XX16
X: Indeterminate Blank spaces are reserved. No access is allowed.
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4. Special Function Registers (SFRs)
Address 031016 031116 031216 031316 031416 031516 031616 031716 031816 031916 031A16 031B16 031C16 031D16 031E16 031F16 032016 032116 032216 032316 032416 032516 032616 032716 032816 032916 032A16 032B16 032C16 032D16 032E16 032F16 033016 033116 033216 033316 033416 033516 033616 033716 033816 033916 033A16 033B16 033C16 033D16 033E16 033F16 Timer B3 Register Timer B4 Register Timer B5 Register
Register
Symbol TB3 TB4 TB5
Value after RESET XX16 XX16 XX16 XX16 XX16 XX16
Timer B3 Mode Register Timer B4 Mode Register Timer B5 Mode Register External Interrupt Request Source Select Register
TB3MR TB4MR TB5MR IFSR
00XX 00002 00XX 00002 00XX 00002 0016
UART3 Special Mode Register 4 UART3 Special Mode Register 3 UART3 Special Mode Register 2 UART3 Special Mode Register UART3 Transmit/Receive Mode Register UART3 Bit Rate Register UART3 Transmit Buffer Register UART3 Transmit/Receive Control Register 0 UART3 Transmit/Receive Control Register 1 UART3 Receive Buffer Register
U3SMR4 U3SMR3 U3SMR2 U3SMR U3MR U3BRG U3TB U3C0 U3C1 U3RB
0016 0016 0016 0016 0016 XX16 XX16 XX16 0000 10002 0000 00102 XX16 XX16
UART2 Special Mode Register 4 UART2 Special Mode Register 3 UART2 Special Mode Register 2 UART2 Special Mode Register UART2 Transmit/Receive Mode Register UART2 Bit Rate Register UART2 Transmit Buffer Register UART2 Transmit/Receive Control Register 0 UART2 Transmit/Receive Control Register 1 UART2 Receive Buffer Register
U2SMR4 U2SMR3 U2SMR2 U2SMR U2MR U2BRG U2TB U2C0 U2C1 U2RB
0016 0016 0016 0016 0016 XX16 XX16 XX16 0000 10002 0000 00102 XX16 XX16
X: Indeterminate Blank spaces are reserved. No access is allowed.
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4. Special Function Registers (SFRs)
Address 034016 034116 034216 034316 034416 034516 034616 034716 034816 034916 034A16 034B16 034C16 034D16 034E16 034F16 035016 035116 035216 035316 035416 035516 035616 035716 035816 035916 035A16 035B16 035C16 035D16 035E16 035F16 036016 036116 036216 036316 036416 036516 036616 036716 036816 036916 036A16 036B16 036C16 036D16 036E16 036F16
Register Count Start Flag Clock Prescaler Reset Flag One-Shot Start Flag Trigger Select Register Up/Down Flag
Symbol TABSR CPSRF ONSF TRGSR UDF
Value after RESET 0016 0XXX XXXX2 0016 0016 0016 XX16
Timer A0 Register Timer A1 Register Timer A2 Register Timer A3 Register Timer A4 Register Timer B0 Register Timer B1 Register Timer B2 Register Timer A0 Mode Register Timer A1 Mode Register Timer A2 Mode Register Timer A3 Mode Register Timer A4 Mode Register Timer B0 Mode Register Timer B1 Mode Register Timer B2 Mode Register Timer B2 Special Mode Register Count Source Prescaler Register(1)
TA0 TA1 TA2 TA3 TA4 TB0 TB1 TB2 TA0MR TA1MR TA2MR TA3MR TA4MR TB0MR TB1MR TB2MR TB2SC TCSPR
XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 0016 0016 0016 0016 0016 00XX 00002 00XX 00002 00XX 00002 XXXX XXX02 0XXX 00002
UART0 Special Mode Register 4 UART0 Special Mode Register 3 UART0 Special Mode Register 2 UART0 Special Mode Register UART0 Transmit/Receive Mode Register UART0 Bit Rate Register UART0 Transmit Buffer Register UART0 Transmit/Receive Control Register 0 UART0 Transmit/Receive Control Register 1 UART0 Receive Buffer Register
U0SMR4 U0SMR3 U0SMR2 U0SMR U0MR U0BRG U0TB U0C0 U0C1 U0RB
0016 0016 0016 0016 0016 XX16 XX16 XX16 0000 10002 0000 00102 XX16 XX16
X: Indeterminate Blank spaces are reserved. No access is allowed. NOTE: 1. The TCSPR register maintains values set before reset, even after software reset or watchdog timer reset has been performed.
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4. Special Function Registers (SFRs)
Address 037016 037116 037216 037316 037416 037516 037616 037716 037816 037916 037A16 037B16 037C16 037D16 037E16 037F16 038016 038116 038216 038316 038416 038516 038616 038716 038816 038916 038A16 038B16 038C16 038D16 038E16 038F16 039016 039116 039216 039316 039416 039516 039616 039716 039816 039916 039A16 039B16 039C16 039D16 039E16 039F16
Register
Symbol
Value after RESET
DMA0 Request Source Select Register DMA1 Request Source Select Register DMA2 Request Source Select Register DMA3 Request Source Select Register CRC Data Register CRC Input Register
DM0SL DM1SL DM2SL DM3SL CRCD CRCIN
0X00 00002 0X00 00002 0X00 00002 0X00 00002 XX16 XX16 XX16 XXXX XXXX2 0000 00002 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16
A/D0 Register 0 A/D0 Register 1 A/D0 Register 2 A/D0 Register 3 A/D0 Register 4 A/D0 Register 5 A/D0 Register 6 A/D0 Register 7
AD00 AD01 AD02 AD03 AD04 AD05 AD06 AD07
A/D0 Control Register 2 A/D0 Control Register 3 A/D0 Control Register 0 A/D0 Control Register 1 D/A Register 0 D/A Register 1 D/A Control Register
AD0CON2 AD0CON3 AD0CON0 AD0CON1 DA0 DA1 DACON
XX0X XXX02 XXXX X0002 0016 0016 XX16 XX16 XXXX XX002
X: Indeterminate Blank spaces are reserved. No access is allowed.
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4. Special Function Registers (SFRs)
Address 03A016 03A116 03A216 03A316 03A416 03A516 03A616 03A716 03A816 03A916 03AA16 03AB16 03AC16 03AD16 03AE16 03AF16 03B016 03B116 03B216 03B316 03B416 03B516 03B616 03B716 03B816 03B916 03BA16 03BB16 03BC16 03BD16 03BE16 03BF16 03C016 03C116 03C216 03C316 03C416 03C516 03C616 03C716 03C816 03C916 03CA16 03CB16 03CC16 03CD16 03CE16 03CF16
Register
Symbol
Value after RESET
Function Select Register D1
PSD1
X0XX XX002
Function Select Register C3 Function Select Register C Function Select Register A0 Function Select Register A1 Function Select Register B0 Function Select Register B1 Function Select Register A2 Function Select Register A3 Function Select Register B2 Function Select Register B3
PSC3 PSC PS0 PS1 PSL0 PSL1 PS2 PS3 PSL2 PSL3
X0XX XXXX2 00X0 00002 0016 0016 0016 0016 00X0 00002 0016 00X0 00002 0016
Port P6 Register Port P7 Register Port P6 Direction Register Port P7 Direction Register Port P8 Register Port P9 Register Port P8 Direction Register Port P9 Direction Register Port P10 Register Port P10 Direction Register
P6 P7 PD6 PD7 P8 P9 PD8 PD9 P10 PD10
XX16 XX16 0016 0016 XX16 XX16 00X0 00002 0016 XX16 0016
X: Indeterminate Blank spaces are reserved. No access is allowed.
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4. Special Function Registers (SFRs)
Address 03D016 03D116 03D216 03D316 03D416 03D516 03D616 03D716 03D816 03D916 03DA16 03DB16 03DC16 03DD16 03DE16 03DF16 03E016 03E116 03E216 03E316 03E416 03E516 03E616 03E716 03E816 03E916 03EA16 03EB16 03EC16 03ED16 03EE16 03EF16 03F016 03F116 03F216 03F316 03F416 03F516 03F616 03F716 03F816 03F916 03FA16 03FB16 03FC16 03FD16 03FE16 03FF16
Register
Symbol
Value after RESET
Pull-Up Control Register 2 Pull-Up Control Register 3
PUR2 PUR3
0016 0016
Port P0 Register(1) Port P1 Register(1) Port P0 Direction Register(1) Port P1 Direction Register(1) Port P2 Register(1) Port P3 Register(1) Port P2 Direction Register(1) Port P3 Direction Register(1) Port P4 Register(1) Port P5 Register(1) Port P4 Direction Register(1) Port P5 Direction Register(1)
P0 P1 PD0 PD1 P2 P3 PD2 PD3 P4 P5 PD4 PD5
XX16 XX16 0016 0016 XX16 XX16 0016 0016 XX16 XX16 0016 0016
Pull-up Control Register 0 Pull-up Control Register 1
PUR0 PUR1
0016 XXXX 00002
Port Control Register
PCR
XXXX XXX02
X: Indeterminate Blank spaces are reserved. No access is allowed. NOTE: 1. Pins, functioning as bus control pins, cannot be selected as I/O ports.
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5. Electrical Characteristics
5. Electrical Characteristics
Table 5.1 Absolute Maximum Ratings
Symbol VCC1, VCC2 VCC2 AVCC VI Supply Voltage Supply Voltage Analog Supply Voltage Input Voltage RESET, CNVSS, BYTE, P60-P67, P72-P77, P80-P87, P90-P97, P100-P107, VREF, XIN P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57 P70, P71 VO Output Voltage P60-P67, P72-P77, P80-P84, P86, P87, P90-P97, P100-P107, XOUT P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57 P70, P71 Pd Topr Tstg Power Dissipation Operating Ambient Temperature Storage Temperature Topr=25 C Parameter Condition VCC1=AVCC VCC1=AVCC Value -0.3 to 6.0 -0.3 to VCC1 -0.3 to 6.0 -0.3 to VCC1+0.3 Unit V V V V
-0.3 to VCC2+0.3 -0.3 to 6.0 -0.3 to VCC1+0.3 -0.3 to VCC2+0.3 -0.3 to 6.0 500 -20 to 85/ -40 to 85(1) -65 to 150 mW C C V
NOTE: 1. Contact our sales office if temperature range of -40 to 85 C is required.
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5. Electrical Characteristics
Table 5.2 Recommended Operating Conditions (VCC1= VCC2=3.0V to 5.5V at Topr=- 20 to 85oC unless otherwise specified)
Symbol VCC1, VCC2 AVCC VSS AVSS VIH Supply Voltage (VCC1 VCC2) Analog Supply Voltage Supply Voltage Analog Supply Voltage Input High ("H") Voltage P20-P27, P30-P37, P40-P47, P50-P57 P60-P67, P72-P77, P80-P87(3), P90-P97, P100-P107, XIN, RESET, CNVSS, BYTE P70, P71 P00-P07, P10-P17 (in single-chip mode) P00-P07, P10-P17 (in memory expansion mode and microprocesor mode) P20-P27, P30-P37, P40-P47, P50-P57 P90-P97, P100-P107, XIN, RESET, CNVSS, BYTE P00-P07, P10-P17 (in single-chip mode) P60-P67, P70-P77, P80-P87(3), 0.8VCC2 0.8VCC1 0.8VCC1 0.8VCC2 0.5VCC2 0 0 0 0 Parameter Standard Min. 3.0 Typ. 5.0 VCC1 0 0 VCC2 VCC1 6.0 VCC2 VCC2 0.2VCC2 0.2VCC1 0.2VCC2 0.16VCC2 -10.0 mA V Max. 5.5 Unit V V V V V
VIL
Input Low ("L") Voltage
IOH(peak)
IOH(avg)
IOL(peak)
IOL(avg)
P00-P07, P10-P17 (in memory expansion mode and microprocesor mode) Peak Output High P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, ("H") Current(2) P60-P67, P72-P77, P80-P84, P86, P87, P90-P97, P100-P107 Average Output P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, High ("H") Current(1) P60-P67, P72-P77, P80-P84, P86, P87, P90-P97, P100-P107 Peak Output Low P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, ("L") Current(2) P60-P67, P70-P77, P80-P84, P86, P87, P90-P97, P100-P107 Average Output Low P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, ("L") Current(1) P60-P67, P70-P77, P80-P84, P86, P87, P90-P97, P100-P107
-5.0
mA
10.0
mA
5.0
mA
NOTES: 1. Typical values when average output current is 100 ms. 2. Total IOL(peak) for P0, P1, P2, P86, P87, P9, and P10 must be 80 mA or less. Total IOL(peak) for P3, P4, P5, P6, P7, and P80 to P84 must be 80 mA or less. Total IOH(peak) for P0, P1, and P2 must be -40 mA or less. Total IOH(peak) for P86, P87, P9, and P10 must be -40 mA or less. Total IOH(peak) for P3, P4, and P5 must be -40 mA or less. Total IOH(peak) for P6, P7, and P80 to P84 must be -40 mA or less. 3. VIH and VIL reference for P87 applies when P87 is used as a programmable input port. It does not apply when P87 is used as XCIN.
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5. Electrical Characteristics
Table 5.2 Recommended Operating Conditions (Continued) (VCC1=VCC2=3.0V to 5.5V at Topr=-20 to 85oC unless otherwise specified)
Symbol f(BCLK) CPU Operation Frequency Parameter VCC1=4.2 to 5.5 V VCC1=3.0 to 5.5 V f(XIN) Main Clock Input Frequency VCC1=4.2 to 5.5 V VCC1=3.0 to 5.5 V f(XCIN) f(Ring) f(PLL) Sub Clock Frequency On-chip Oscillator Frequency (Topr=25 C) PLL Clock Frequency VCC1=4.2 to 5.5 V VCC1=3.0 to 5.5 V tSU(PLL) Wait Time to Stabilize PLL Frequency Synthesizer VCC1=5.0 V VCC1=3.3 V 0.5 10 10 Standard Min. 0 0 0 0 32.768 1 Typ. Max. 32 24 32 24 50 2 32 24 5 10 Unit MHz MHz MHz MHz kHz MHz MHz MHz ms ms
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5. Electrical Characteristics
VCC1=VCC2=5V
Table 5.3 Electrical Characteristics (VCC1=VCC2=4.2 to 5.5V, VSS=0V at Topr= -20 to 85oC, f(BCLK)=32MHZ unless otherwise specified)
Symbol VOH Output High ("H") Voltage Parameter P00-P07, P10-P17, P50-P57 P60-P67, P72-P77, P97, P100-P107 P00-P07, P10-P17, P50-P57 P60-P67, P72-P77, P97, P100-P107 XOUT XCOUT Condition P20-P27, P30-P37, P40-P47, IOH=-5mA P80-P84, P86, P87, P90IOH=-5mA Standard Min. VCC2-2.0 VCC1-2.0 VCC2-0.3 VCC1-0.3 3.0 2.5 1.6 2.0 V Typ. Max. VCC2 VCC1 VCC2 VCC1 VCC1 V V V Unit V
P20-P27, P30-P37, P40-P47, IOH=-200A P80-P84, P86, P87, P90IOH=-200A IOH=-1mA High Power Low Power No load applied No load applied
VOL
Output Low ("L") Voltage
P00-P07, P10-P17, P20-P27, P50-P57, P60-P67, P70-P77, P87, P90-P97, P100-P107 P00-P07, P10-P17, P20-P27, P50-P57, P60-P67, P70-P77, P87, P90-P97, P100-P107 XOUT XCOUT
P30-P37, P40-P47, IOL=5mA P80-P84, P86, P30-P37, P40-P47, IOL=200A P80-P84, P86, IOL=1mA No load applied No load applied 0.2 0 0
0.45
V
2.0
V V
High Power Low Power
VT+-VT- Hysteresis
HOLD, RDY, TA0IN-TA4IN, TB0IN-TB5IN, INT0-INT5, ADTRG, CTS0-CTS4, CLK0-CLK4, TA0OUT-TA4OUT, NMI, KI0-KI3, RxD0-RxD4, SCL0-SCL4, SDA0-SDA4 RESET
1.0
V
0.2 VI=5V
IIH
Input High ("H") Current
P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P67, P70-P77, P80-P87, P90-P97, P100-P107, XIN, RESET, CNVSS, BYTE
1.8 5.0
V A
IIL
Input Low ("L") Current
P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, VI=0V P50-P57, P60-P67, P70-P77, P80-P87, P90-P97, P100-P107, XIN, RESET, CNVSS, BYTE P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, VI=0V P50-P57, P60-P67, P72-P77, P80-P84, P86, P87, P90-P97, P100-P107 XIN XCIN In stop mode In single-chip mode, output pins are left open and other pins are connected to VSS. 20 40
-5.0
A
RPULLUP Pull-up Resistance
167
k
RfXIN RfXCIN VRAM I CC
Feedback Resistance Feedback Resistance RAM Standby Voltage Power Supply Current
1.5 15 2.0 f(BCLK)=32 MHz, Square wave, No division f(BCLK)=32 kHz, In wait mode, Topr=25 C While clock stops, Topr=25 C While clock stops, Topr=85 C 22 10 0.8 5 20 60
M M V mA A A A
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M32C/80 Group
5. Electrical Characteristics
VCC1=VCC2=5V
Table 5.4 A/D Conversion Characteristics (VCC1=VCC2=AVCC=VREF=4.2 to 5.5V, Vss= AVSS = 0V at Topr=-20 to 85oC, f(BCLK) = 32MHZ unless otherwise specified)
Symbol Resolution Parameter VREF=VCC1 AN0 to AN7, ANEX0, ANEX1 INL Integral Nonlinearity Error VREF=VCC1=VCC2=5V External op-amp connection mode DNL RLADDER tCONV tCONV tSAMP VREF VIA Differential Nonlinearity Error Offset Error Gain Error Resistor Ladder 10-bit Conversion Time(1, 2) 8-bit Conversion Sampling Time(1) Reference Voltage Analog Input Voltage Time(1, 2) VREF=VCC1 8 2.06 1.75 0.188 2 0 VCC1 VREF 7 1 3 3 40 Measurement Condition Standard Min. Typ. Max. 10 3 Bits LSB LSB LSB LSB LSB LSB LSB k s s s V V Unit
NOTES: 1. Divide f(XIN), if exceeding 16 MHz, to keep AD frequency at 16 MHz or less. 2. With using the sample and hold function.
Table 5.5 D/A Conversion Characteristics (VCC1=VCC2=VREF=4.2 to 5.5V, VSS=AVSS=0V at Topr=-20 to 85oC, f(BCLK) = 32MHZ unless otherwise specified)
Symbol tSU RO IVREF Resolution Absolute Accuracy Setup Time Output Resistance Reference Power Supply Input Current (Note 1) 4 10 Parameter Measurement Condition Min. Standard Typ. Max. 8 1.0 3 20 1.5 Bits % s k mA Unit
NOTE: 1. Measurement when using one D/A converter. The DAi register (i=0, 1) of the D/A converter, not being used, is set to "0016". The resistor ladder in the A/D converter is excluded. IVREF flows even if the VCUT bit in the AD0CON1 register is set to "0" (no VREF connection).
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5. Electrical Characteristics
VCC1=VCC2=5V
Timing Requirements (VCC1=VCC2=4.2 to 5.5V, VSS=0V at Topr=-20 to 85oC unless otherwise specified) Table 5.6 External Clock Input
Symbol tc tw(H) tw(L) tr tf Parameter External Clock Input Cycle Time External Clock Input High ("H") Width External Clock Input Low ("L") Width External Clock Rise Time External Clock Fall Time Standard Min. 31.25 13.75 13.75 5 5 Max. Unit ns ns ns ns ns
Table 5.7 Memory Expansion Mode and Microprocessor Mode
Symbol tac1(RD-DB) tac1(AD-DB) tac2(RD-DB) tac2(AD-DB) tsu(DB-BCLK) tsu(RDY-BCLK) Data Input Access Time (RD standard) Data Input Access Time (AD standard, CS standard) Data Input Access Time (RD standard, when accessing a space with the multiplexrd bus) Data Input Access Time (AD standard, when accessing a space with the multiplexed bus) Data Input Setup Time RDY Input Setup Time 26 26 30 0 0 0 25 Parameter Standard Min. Max. (Note 1) (Note 1) (Note 1) (Note 1) Unit ns ns ns ns ns ns ns ns ns ns ns
tsu(HOLD-BCLK) HOLD Input Setup Time th(RD-DB) th(BCLK-RDY) th(BCLK-HOLD) td(BCLK-HLDA) Data Input Hold Time RDY Input Hold Time HOLD Input Hold Time HLDA Output Delay Time
NOTE: 1. Values can be obtained from the following equations, according to BCLK frequecncy and external bus cycles. Insert a wait state or lower the operation frequency, f(BCLK), if the calculated value is negative.
10 X m tac1(RD - DB) = f(BCLK) X 2 tac1(AD - DB) = tac2(RD - DB) = tac2(AD - DB) = 109 X n f(BCLK) 10 X m f(BCLK) X 2
9
9
- 35 - 35 - 35
[ns] (if external bus cycle is a + b, m=(bx2)+1) [ns] (if external bus cycle is a + b, n=a+b) [ns] (if external bus cycle is a + b, m=(bx2)-1) [ns] (if external bus cycle is a + b, p={(a+b-1)x2}+1)
109 X p - 35 f(BCLK) X 2
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5. Electrical Characteristics
VCC1=VCC2=5V
Timing Requirements (VCC1=VCC2=4.2 to 5.5V, VSS=0V at Topr=-20 to 85oC unless otherwise specified) Table 5.8 Timer A Input (Count Source Input in Event Counter Mode)
Symbol tc(TA) tw(TAH) tw(TAL) TAiIN Input Cycle Time TAiIN Input High ("H") Width TAiIN Input Low ("L") Width Parameter Standard Min. 100 40 40 Max. ns ns ns Unit
Table 5.9 Timer A Input (Gate Input in Timer Mode)
Standard Symbol tc(TA) tw(TAH) tw(TAL) TAiIN Input Cycle Time TAiIN Input High ("H") Width TAiIN Input Low ("L") Width Parameter Min. 400 200 200 Max. Unit ns ns ns
Table 5.10 Timer A Input (External Trigger Input in One-Shot Timer Mode)
Standard Symbol tc(TA) tw(TAH) tw(TAL) TAiIN Input Cycle Time TAiIN Input High ("H") Width TAiIN Input Low ("L") Width Parameter Min. 200 100 100 Max. ns ns ns Unit
Table 5.11 Timer A Input (External Trigger Input in Pulse Width Modulation Mode)
Standard Symbol tw(TAH) tw(TAL) TAiIN Input High ("H") Width TAiIN Input Low ("L") Width Parameter Min. 100 100 Max. ns ns Unit
Table 5.12 Timer A Input (Counter Increment/Decrement Input in Event Counter Mode)
Standard Symbol tc(UP) tw(UPH) tw(UPL) tsu(UP-TIN) th(TIN-UP) TAiOUT Input Cycle Time TAiOUT Input High ("H") Width TAiOUT Input Low ("L") Width TAiOUT Input Setup Time TAiOUT Input Hold Time Parameter Min. 2000 1000 1000 400 400 Max. ns ns ns ns ns Unit
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5. Electrical Characteristics
VCC1=VCC2=5V
Timing Requirements (VCC1 = VCC2 = 4.2 to 5.5V, VSS = 0V at Topr = -20 to 85oC unless otherwise specified) Table 5.13 Timer B Input (Count Source Input in Event Counter Mode)
Symbol tc(TB) tw(TBH) tw(TBL) tc(TB) tw(TBH) tw(TBL) Parameter TBiIN Input Cycle Time (counted on one edge) TBiIN Input High ("H") Width (counted on one edge) TBiIN Input Low ("L") Width (counted on one edge) TBiIN Input Cycle Time (counted on both edges) TBiIN Input High ("H") Width (counted on both edges) TBiIN Input Low ("L") Width (counted on both edges) Standard Min. 100 40 40 200 80 80 Max. Unit ns ns ns ns ns ns
Table 5.14 Timer B Input (Pulse Period Measurement Mode)
Symbol tc(TB) tw(TBH) tw(TBL) TBiIN Input Cycle Time TBiIN Input High ("H") Width TBiIN Input Low ("L") Width Parameter Standard Min. 400 200 200 Max. Unit ns ns ns
Table 5.15 Timer B Input (Pulse Width Measurement Mode)
Standard Symbol tc(TB) tw(TBH) tw(TBL) TBiIN Input Cycle Time TBiIN Input High ("H") Width TBiIN Input Low ("L") Width Parameter Min. 400 200 200 Max. ns ns ns Unit
Table 5.16 A/D Trigger Input
Symbol tc(AD) tw(ADL) Parameter ADTRG Input Cycle Time (required for trigger) ADTRG Input Low ("L") Width Standard Min. 1000 125 Max Unit ns ns
Table 5.17 Serial I/O
Symbol tc(CK) tw(CKH) tw(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-Q) CLKi Input Cycle Time CLKi Input High ("H") Width CLKi Input Low ("L") Width TxDi Output Delay Time TxDi Hold Time RxDi Input Setup Time RxDi Input Hold Time
_______
Parameter
Standard Min. 200 100 100 80 0 30 90 Max.
Unit ns ns ns ns ns ns ns
Table 5.18 External Interrupt INTi Input
Symbol tw(INH) tw(INL) INTi Input High ("H") Width INTi Input Low ("L") Width Parameter Standard Min. 250 250 Max. Unit ns ns
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5. Electrical Characteristics
VCC1=VCC2=5V
Switching Characteristics (VCC1 = VCC2 = 4.2 to 5.5V, VSS = 0V at Topr = -20 to 85oC unless otherwise specified) Table 5.19 Memory Expansion Mode and Microprocessor Mode (when accessing external memory space)
Symbol td(BCLK-AD) th(BCLK-AD) th(RD-AD) th(WR-AD) td(BCLK-CS) th(BCLK-CS) th(RD-CS) th(WR-CS) td(BCLK-RD) th(BCLK-RD) td(BCLK-WR) th(BCLK-WR) td(DB-WR) th(WR-DB) tw(WR) Parameter Address Output Delay Time Address Output Hold Time (BCLK standard) Address Output Hold Time (RD standard) Address Output Hold Time (WR standard) Chip-Select Signal Output Delay Time Chip-Select Signal Output Hold Time (BCLK standard) Chip-Select Signal Output Hold Time (RD standard) Chip-Select Signal Output Hold Time (WR standard) RD Signal Output Delay Time RD Signal Output Hold Time WR Signal Output Delay Time WR Signal Output Hold Time Data Output Delay Time (WR standard) Data Output Hold Time (WR standard) WR Output Width -5 (Note 2) (Note 1) (Note 2) -5 18 -3 0 (Note 1) 18 -3 0 (Note 1) 18 Measurement Condition Standard Min. Max. 18 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
See Figure 5.1
NOTES: 1. Values can be obtained from the following equations, according to BCLK frequency. 10 9 th(WR - DB) = - 10 [ns] f(BCLK) X 2 9 10 th(WR - AD) = - 10 [ns] f(BCLK) X 2 th(WR - CS) = 10 9 f(BCLK) X 2 - 10 [ns]
2. Values can be obtained from the following equations, according to BCLK frequency and external bus cycles. tw(WR) = td(DB - WR) = 10 X n f(BCLK) X 2 10 X m f(BCLK)
9 9
- 15 - 20
[ns] [ns]
(if external bus cycle is a + b, n=(bx2)-1) (if external bus cycle is a + b, m= b)
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5. Electrical Characteristics
VCC1=VCC2=5V
Switching Characteristics (VCC = 4.2 to 5.5V, VSS = 0V at Topr = -20 to 85oC unless otherwise specified) Table 5.20 Memory Expansion Mode and Microprocessor Mode (when accessing an external memory space with the multiplexed bus)
Symbol td(BCLK-AD) th(BCLK-AD) th(RD-AD) th(WR-AD) td(BCLK-CS) th(BCLK-CS) th(RD-CS) th(WR-CS) td(BCLK-RD) th(BCLK-RD) td(BCLK-WR) th(BCLK-WR) td(DB-WR) th(WR-DB) td(BCLK-ALE) th(BCLK-ALE) td(AD-ALE) th(ALE-AD) tdz(RD-AD) Parameter Address Output Delay Time Address Output Hold Time (BCLK standard) Address Output Hold Time (RD standard) Address Output Hold Time (WR standard) Chip-Select Signal Output Delay Time Chip-Select Signal Output Hold Time (BCLK standard) Chip-Select Signal Output Hold Time (RD standard) Chip-Select Signal Output Hold Time (WR standard) RD Signal Output Delay Time RD Signal Output Hold Time WR Signal Output Delay Time WR Signal Output Hold Time Data Output Delay Time (WR standard) Data Output Hold Time (WR standard) ALE Signal Output Delay Time (BCLK standard) ALE Signal Output Hold Time (BCLK standard) ALE Signal Output Delay Time (address standard) ALE Signal Output Hold Time (address standard) Address Output Float Start Time -5 (Note 3) (Note 4) 8 -5 (Note 2) (Note 1) 18 -3 (Note 1) (Note 1) -3 (Note 1) (Note 1) 18 Measurement Condition Standard Min. Max. 18 ns ns ns ns ns ns ns ns 18 -5 18 ns ns ns ns ns ns ns ns ns ns ns Unit
See Figure 5.1
NOTES: 1. Values can be obtained from the following equations, according to BCLK frequency. th(RD - AD) = th(WR - AD) = th(RD - CS) = th(WR - CS) = th(WR - DB) = 10 9 f(BCLK) X 2 10 9 f(BCLK) X 2 10 9 f(BCLK) X 2 10 9 f(BCLK) X 2 10 9 f(BCLK) X 2 - 10 - 10 - 10 - 10 - 10 [ns] [ns] [ns] [ns] [ns]
2. Values can be obtained from the following equations, according to BCLK frequency and external bus cycle. td(DB - WR) = 10 X m - 25 f(BCLK) X 2
9
[ns] (if external bus cycle is a + b, m= (bx2)-1)
3. Values can be obtained from the following equations, according to BCLK frequency and external bus cycle. td(AD - ALE) = 10 X n f(BCLK) X 2
9
- 20
[ns] (if external bus cycle is a + b, n= a)
4. Values can be obtained from the following equations, according to BCLK frequency and external bus cycle. th(ALE - AD) = 10 X n f(BCLK) X 2
9
- 10
[ns] (if external bus cycle is a + b, n= a)
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5. Electrical Characteristics
VCC1=VCC2=5V
P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 30pF
Figure 5.1 P0 to P10 Measurement Circuit
Rev. 1.10 Nov. 01, 2005 Page 40 REJ03B0038-0110
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M32C/80 Group
5. Electrical Characteristics
Vcc1=Vcc2=5V
Memory Expansion Mode and Microprocessor Mode
(when accessing an external memory space)
[ Read Timing ] (1 +1 Bus Cycle)
BCLK
td(BCLK-CS)
18ns.max(1) tcyc
th(BCLK-CS)
-3ns.min
CSi
th(RD-CS)
0ns.min
td(BCLK-AD)
ADi BHE
18ns.max(1)
th(BCLK-AD)
-3ns.min
td(BCLK-RD)
18ns.max
th(RD-AD)
0ns.min
RD
tac1(RD-DB)(2) tac1(AD-DB)(2)
DB
Hi-Z
th(BCLK-RD)
-5ns.min
tsu(DB-BCLK)
26ns.min(1)
th(RD-DB)
0ns.min
NOTES: 1. Values guaranteed only when the microcomputer is used independently. A maximum of 35ns is guaranteed for td(BCLK-AD)+tsu(DB-BCLK). 2. Varies with operation frequency: tac1(RD-DB)=(tcyc/2 x m-35)ns.max (if external bus cycle is a + b, m=(b x 2)+1) tac1(AD-DB)=(tcyc x n-35)ns.max (if external bus cycle is a + b, n=a+b)
[ Write timing ] (1 +1 Bus Cycle)
BCLK
td(BCLK-CS)
18ns.max
th(BCLK-CS)
-3ns.min
CSi
tcyc
th(WR-CS)(3) th(BCLK-AD)
-3ns.min
td(BCLK-AD)
18ns.max
ADi BHE
td(BCLK-WR)
WR,WRL, WRH
18ns.max
tw(WR)(3)
th(WR-AD)(3) th(BCLK-WR)
-5ns.min
td(DB-WR)(3)
DBi
th(WR-DB)(3)
NOTE: 3. Varies with operation frequency: td(DB-WR)=(tcyc x m-20)ns.min (if external bus cycle is a+b, m=b) th(WR-DB)=(tcyc/2-10)ns.min th(WR-AD)=(tcyc/2-10)ns.min th(WR-CS)=(tcyc/2-10)ns.min tw(WR)=(tcyc/2 x n-15)ns.min (if external bus cycle is a+b , n=(bx2)-1)
Measurement Conditions: * VCC1=VCC2=4.2 to 5.5V * Input high and low voltage: VIH=2.5V, VIL=0.8V * Output high and low voltage: VOH=2.0V, VOL=0.8V tcyc= 10 f(BCLK)
9
Figure 5.2 VCC1=VCC2=5V Timing Diagram (1)
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5. Electrical Characteristics
Memory Expansion Mode and Microprocessor Mode
(when accessing an external memory space with the multiplexed bus) [ Read Timing ] (2 +2 Bus Cycle)
BCLK
Vcc1=Vcc2=5V
td(BCLK-ALE)
18ns.max
th(BCLK-ALE)
-5ns.min
ALE
td(BCLK-CS)
18ns.max
tcyc
th(BCLK-CS)
-3ns.min
CSi
th(RD-CS)(1) td(AD-ALE)(1) th(ALE-AD)
Address
(1)
tsu(DB-BCLK) 26ns.min tdz(RD-AD)
8ns.max
ADi /DBi
Data input
Address
td(BCLK-AD)
ADi BHE
18ns.max
tac2(RD-DB)(1)
(1)
th(RD-DB)
0ns.min
th(BCLK-AD)
-3ns.min
tac2(AD-DB)
RD
td(BCLK-RD)
18ns.max
th(BCLK-RD)
-5ns.min
th(RD-AD)
(1)
NOTE: 1. Varies with operation frequency: td(AD-ALE)=(tcyc/2 x n-20)ns.min (if external bus cycle is a + b, n=a) th(ALE-AD)=(tcyc/2 x n-10)ns.min (if external bus cycle is a + b, n=a) th(RD-AD)=(tcyc/2-10)ns.min, th(RD-CS)=(tcyc/2-10)ns.min tac2(RD-DB)=(tcyc/2 x m-35)ns.max (if external bus cycle is a + b, m=(b x 2)-1) tac2(AD-DB)=(tcyc/2 x p-35)ns.max (if external bus cycle is a + b, p={(a+b-1) x 2}+1)
[ Write Timing ] (2 +2 Bus Cycle)
BCLK
td(BCLK-ALE)
18ns.max
th(BCLK-ALE)
-5ns.min
ALE
td(BCLK-CS)
18ns.max
tcyc
th(WR-CS)
(2)
th(BCLK-CS)
-3ns.min
CSi
td(AD-ALE)
ADi /DBi
(2)
th(ALE-AD)
Address
(2)
Data output
Address
td(BCLK-AD)
ADi BHE
18ns.max
td(DB-WR)
(2)
th(WR-DB)
(2)
th(BCLK-AD)
-3ns.min
td(BCLK-WR)
WR,WRL, WRH NOTE: 2. Varies with operation frequency: td(AD-ALE)=(tcyc/2 x n - 20)ns.min (if external bus cycle is a + b, n=a) th(ALE-AD)=(tcyc/2 x n -10)ns.min (if external bus cycle is a + b, n=a) th(WR-AD)=(tcyc/2-10)ns.min, th(WR-CS)=(tcyc/2-10)ns.min, th(WR-DB)=(tcyc/2-10)ns.min td(DB-WR)=(tcyc/2 x m-25)ns.min (if external bus cycle is a + b, m=(b x 2)-1)
18ns.max
th(BCLK-WR)
-5ns.min
th(WR-AD) (2)
Measurement Conditions: * VCC1=VCC2=4.2 to 5.5V * Input high and low voltage: VIH=2.5V, VIL=0.8V * Output high and low voltage: VOH=2.0V, VOL=0.8V 9 tcyc= 10 f(BCLK)
Figure 5.3 VCC1=VCC2=5V Timing Diagram (2)
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M32C/80 Group
5. Electrical Characteristics
tc(TA) tw(TAH) TAiIN Input tw(TAL) tc(UP) tw(UPH) TAiOUT Input tw(UPL) TAiOUT Input (Counter increment/ decrement input) In event counter mode TAiIN Input
(When counting on the falling edge)
Vcc1=Vcc2=5V
th(TIN-UP)
tsu(UP-TIN)
TAiIN Input
(When counting on the rising edge)
tc(TB) tw(TBH) TBiIN Input tw(TBL) tc(AD) tw(ADL) ADTRG Input tc(CK) tw(CKH) CLKi tw(CKL) TxDi td(C-Q) RxDi tw(INL) INTi Input tw(INH) tsu(D-C) th(C-D) th(C-Q)
NMI input
2 CPU clock cycles + 300ns or more ("L" width) 2 CPU clock cycles + 300ns or more
Figure 5.4 VCC1=VCC2=5V Timing Diagram (3)
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5. Electrical Characteristics
Vcc1=Vcc2=5V
Memory Expansion Mode and Microprocessor Mode
BCLK RD (Separate bus) WR, WRL, WRH (Separate bus) RD (Multiplexed bus) WR, WRL, WRH (Multiplexed bus) RDY input tsu(RDY-BCLK) th(BCLK-RDY)
BCLK tsu(HOLD-BCLK) HOLD Input th(BCLK-HOLD)
HLDA Output P0, P1, P2, P3, P4, P50 to P52
td(BCLK-HLDA)
Hi-Z
td(BCLK-HLDA)
Measurement Conditions * VCC1=VCC2=4.2 to 5.5V * Input high and low voltage: VIH=4.0V, VIL=1.0V * Output high and low voltage: VOH=2.5V, VOL=2.5V
Figure 5.5 VCC1=VCC2=5V Timing Diagram (4)
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5. Electrical Characteristics
VCC1=VCC2=3.3V
Table 5.21 Electrical Characteristics (VCC1=VCC2=3.0 to 3.6V, VSS=0V at Topr = -20 to 85oC, f(BCLK)=24MHZ unless otherwise specified)
Symbol VOH Output High ("H") Voltage Parameter Condition Standard Min. Typ. VCC2-0.6 VCC1-0.6 IOH=-0.1mA High Power Low Power VOL Output Low ("L") Voltage P00-P07, P10-P17, P20-P27, P30-P37, P40P47, P50-P57, P60-P67, P70-P77, P80-P84, P86, P87, P90-P97, P100-P107 XOUT XCOUT High Power Low Power VT+-VT- Hysteresis HOLD, RDY, TA0IN-TA4IN, TB0IN-TB5IN, INT0-INT5, ADTRG, CTS0-CTS4, CLK0CLK4, TA0OUT-TA4OUT, NMI, KI0-KI3, RxD0RxD4, SCL0-SCL4, SDA0-SDA4 RESET IIH Input High ("H") Current P00-P07, P10-P17, P20-P27, P30-P37, P40P47, P50-P57, P60-P67, P70-P77, P80-P87, P90-P97, P100-P107, XIN, RESET, CNVSS, BYTE P00-P07, P10-P17, P20-P27, P30-P37, P40P47, P50-P57, P60-P67, P70-P77, P80-P87, P90-P97, P100-P107, XIN, RESET, CNVSS, BYTE RPULLUP Pull-up Resistance P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, VI=0V P50-P57, P60-P67, P72-P77, P80-P84, P86, P87, P90-P97, P100-P107 RfXIN RfXCIN VRAM ICC Feedback Resistance Feedback Resistance RAM Standby Voltage Power Supply Current XIN XCIN in stop mode Measurement condition: In single-chip mode, output pins are left open and other pins are connected to VSS. 3.0 30.0 2.0 f(BCLK)=24 MHz, Square wave, No division f(BCLK)=32 kHz, In wait mode, Topr=25 C While clock stops, Topr=25 C While clock stops, Topr=85 C 17 10 0.8 5 50 35 M M V mA A A A 40 70 500 k VI=3V 0.2 1.8 4.0 V A No load applied No load applied IOL=1mA 2.7 2.5 1.6 0.5 Max. VCC2 VCC1 VCC1 Unit V V V V V V
P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, IOH=-1mA P50-P57 P60-P67, P72-P77, P80-P84, P86, P87, P90P97, P100-P107 XOUT XCOUT
IOL=0.1mA No load applied No load applied 0.2 0 0
0.5
V V V
1.0
V
IIL
Input Low ("L") Current
VI=0V
-4.0
A
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M32C/80 Group
5. Electrical Characteristics
VCC1=VCC2=3.3V
Table 5.22 A/D Conversion Characteristics (VCC1=VCC2=AVCC=VREF= 3.0 to 3.6V, VSS=AVSS=0V at Topr = -20 to 85oC, f(BCLK) = 24MHZ unless otherwise specified)
Symbol INL DNL RLADDER tCONV VREF VIA Resolution Integral Nonlinearity Error Differential Nonlinearity Error Offset Error Gain Error Resistor Ladder 8-bit Conversion Time(1, 2) No S&H (8-bit) No S&H (8-bit) No S&H (8-bit) No S&H (8-bit) VREF=VCC1 8.0 6.1 3.3 0 VCC1 VREF Parameter Measurement Condition VREF=VCC1 VCC1=VCC2=VREF=3.3V Standard Min. Typ. Max. 10 2 1 2 2 40 Bits LSB LSB LSB LSB k s V V Unit
Reference Voltage Analog Input Voltage
S&H: Sample and Hold NOTES: 1. Divide f(XIN), if exceeding 10 MHz, to keep AD frequency at 10 MHz or less. 2. S&H not available.
Table 5.23 D/A Conversion Characteristics (VCC1=VCC2=VREF=3.0 to 3.6V, VSS=AVSS=0V at Topr = -20 to 85oC, f(BCLK) = 24MHZ unless otherwise specified)
Symbol tSU RO IVREF Resolution Absolute Accuracy Setup Time Output Resistance Reference Power Supply Input Current (Note 1) 4 10 Parameter Measurement Condition Standard Min. Typ. Max. 8 1.0 3 20 1.0 Bits % s k mA Unit
NOTE: 1. Measurement results when using one D/A converter. The DAi register (i=0, 1) of the D/A converter, not being used, is set to "0016". The resistor ladder in the A/D converter is excluded. IVREF flows even if the VCUT bit in the AD0CON1 register is set to "0" (no VREF connection).
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M32C/80 Group
5. Electrical Characteristics
VCC1=VCC2=3.3V
Timing Requirements (VCC1=VCC2= 3.0 to 3.6V, VSS = 0V at Topr = -20 to 85oC unless otherwise specified) Table 5.24 External Clock Input
Symbol tc tw(H) tw(L) tr tf External Clock Input Cycle Time External Clock Input High ("H") Width External Clock Input Low ("L") Width External Clock Rise Time External Clock Fall Time Parameter Standard Min. 41 18 18 5 5 Max. Unit ns ns ns ns ns
Table 5.25 Memory Expansion Mode and Microprocessor Mode
Symbol tac1(RD-DB) tac1(AD-DB) tac2(RD-DB) tac2(AD-DB) tsu(DB-BCLK) tsu(RDY-BCLK) th(RD-DB) th(BCLK-RDY) th(BCLK-HOLD) td(BCLK-HLDA) Data Input Access Time (RD standard) Data Input Access Time (AD standard, CS standard) Data Input Access Time (RD standard, when accessing a space with the multiplexed bus) Data Input Access Time (AD standard, when accessing a space with the multiplexed bus) Data Input Setup Time RDY Input Setup Time Data Input Hold Time RDY Input Hold Time HOLD Input Hold Time HLDA Output Delay Time 30 40 60 0 0 0 25 Parameter Standard Min. Max. (Note 1) (Note 1) (Note 1) (Note 1) Unit ns ns ns ns ns ns ns ns ns ns ns
tsu(HOLD-BCLK) HOLD Input Setup Time
NOTE: 1. Values can be obtained from the following equations, according to BCLK frequecncy and external bus cycles. Insert a wait state or lower the operation frequency, f(BCLK), if the calculated value is negative.
10 X m tac1(RD - DB) = f(BCLK) X 2 tac1(AD - DB) = tac2(RD - DB) = tac2(AD - DB) = 10 X n f(BCLK) 10 X m f(BCLK) X 2
9 9
9
- 35 - 35 - 35
[ns] (if external bus cycle is a + b, m=(bx2)+1) [ns] (if external bus cycle is a + b, n=a+b) [ns] (if external bus cycle is a + b, m=(bx2)-1) [ns] (if external bus cycle is a + b, p={(a+b-1)x2}+1)
109 X p - 35 f(BCLK) X 2
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5. Electrical Characteristics
VCC1=VCC2=3.3V
Timing Requirements (VCC1=VCC2= 3.0 to 3.6V, VSS= 0V at Topr = -20 to 85oC unless otherwise specified) Table 5.26 Timer A Input (Count Source Input in Event Counter Mode)
Symbol tc(TA) tw(TAH) tw(TAL) TAiIN Input Cycle Time TAiIN Input High ("H") Width TAiIN Input Low ("L") Width Parameter Standard Min. 100 40 40 Max. ns ns ns Unit
Table 5.27 Timer A Input (Gate Input in Timer Mode)
Standard Symbol tc(TA) tw(TAH) tw(TAL) TAiIN Input Cycle Time TAiIN Input High ("H") Width TAiIN Input Low ("L") Width Parameter Min. 400 200 200 Max. Unit ns ns ns
Table 5.28 Timer A Input (External Trigger Input in One-Shot Timer Mode)
Standard Symbol tc(TA) tw(TAH) tw(TAL) TAiIN Input Cycle Time TAiIN Input High ("H") Width TAiIN Input Low ("L") Width Parameter Min. 200 100 100 Max. ns ns ns Unit
Table 5.29 Timer A Input (External Trigger Input in Pulse Width Modulation Mode)
Standard Symbol tw(TAH) tw(TAL) TAiIN Input High ("H") Width TAiIN Input Low ("L") Width Parameter Min. 100 100 Max. ns ns Unit
Table 5.30 Timer A Input (Counter Increment/decrement Input in Event Counter Mode)
Standard Symbol tc(UP) tw(UPH) tw(UPL) tsu(UP-TIN) th(TIN-UP) TAiOUT Input Cycle Time TAiOUT Input High ("H") Width TAiOUT Input Low ("L") Width TAiOUT Input Setup Time TAiOUT Input Hold Time Parameter Min. 2000 1000 1000 400 400 Max. ns ns ns ns ns Unit
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5. Electrical Characteristics
VCC1=VCC2=3.3V
Timing Requirements (VCC1=VCC2= 3.0 to 3.6V, VSS = 0V at Topr = -20 to 85oC unless otherwise specified) Table 5.31 Timer B Input (Count Source Input in Event Counter Mode)
Symbol tc(TB) tw(TBH) tw(TBL) tc(TB) tw(TBH) tw(TBL) Parameter TBiIN Input Cycle Time (counted on one edge) TBiIN Input High ("H") Width (counted on one edge) TBiIN Input Low ("L") Width (counted on one edge) TBiIN Input Cycle Time (counted on both edges) TBiIN Input High ("H") Width (counted on both edges) TBiIN Input Low ("L") Width (counted on both edges) Standard Min. 100 40 40 200 80 80 Max. Unit ns ns ns ns ns ns
Table 5.32 Timer B Input (Pulse Period Measurement Mode)
Symbol tc(TB) tw(TBH) tw(TBL) TBiIN Input Cycle Time TBiIN Input High ("H") Wdth TBiIN Input Low ("L") Width Parameter Standard Min. 400 200 200 Max. Unit ns ns ns
Table 5.33 Timer B Input (Pulse Width Measurement Mode)
Standard Symbol tc(TB) tw(TBH) tw(TBL) TBiIN Input Cycle Time TBiIN Input High ("H") Width TBiIN Input Low ("L") Width Parameter Min. 400 200 200 Max. ns ns ns Unit
Table 5.34 A/D Trigger Input
Symbol tc(AD) tw(ADL) Parameter ADTRG Input Cycle Time (required for trigger) ADTRG Input Low ("L") Width Standard Min. 1000 125 Max. Unit ns ns
Table 5.35 Serial I/O
Symbol tc(CK) tw(CKH) tw(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-Q) CLKi Input Cycle Time CLKi Input High ("H") Width CLKi Input Low ("L") Width TxDi Output Delay Time TxDi Hold Time RxDi Input Setup Time RxDi Input Hold Time
_______
Parameter
Standard Min. 200 100 100 80 0 30 90 Max.
Unit ns ns ns ns ns ns ns
Table 5.36 External Interrupt INTi Input
Symbol tw(INH) tw(INL) INTi Input High ("H") Width INTi Input Low ("L") Width Parameter Standard Min. 250 250 Max. Unit ns ns
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5. Electrical Characteristics
VCC1=VCC2=3.3V
Switching Characteristics (VCC1=VCC2=3.0 to 3.6V, VSS = 0V at Topr = -20 to 85oC unless otherwise specified) Table 5.37 Memory Expansion Mode and Microprocessor Mode (when accessing external memory space)
Symbol td(BCLK-AD) th(BCLK-AD) th(RD-AD) th(WR-AD) td(BCLK-CS) th(BCLK-CS) th(RD-CS) th(WR-CS) td(BCLK-RD) th(BCLK-RD) td(BCLK-WR) th(BCLK-WR) td(DB-WR) th(WR-DB) tw(WR) Parameter Address Output Delay Time Address Output Hold Time (BCLK standard) Address Output Hold Time (RD standard) Address Output Hold Time (WR standard) Chip-Select Signal Output Delay Time Chip-Select Signal Output Hold Time (BCLK standard) Chip-Select Signal Output Hold Time (RD standard) Chip-Select Signal Output Hold Time (WR standard) RD Signal Output Delay Time RD Signal Output Hold Time WR Signal Output Delay Time WR Signal Output Hold Time Data Output Delay Time (WR standard) Data Output Hold Time (WR standard) WR Output Width 0 (Note 2) (Note 1) (Note 2) -3 18 0 0 0 (Note 1) 18 Measurement Condition Standard Min. Max. 18 ns ns ns ns ns ns ns ns 18 ns ns ns ns ns ns ns Unit
See Figure 5.1
0 (Note 1)
NOTES: 1. Values can be obtained from the following equations, according to BCLK frequency. th(WR - DB) = th(WR - AD) = th(WR - CS) = 10 9 f(BCLK) X 2 10 9 f(BCLK) X 2 10 9 f(BCLK) X 2 - 20 - 10 - 10 [ns] [ns] [ns]
2. Values can be obtained from the following equations, according to BCLK frequency and external bus cycles. tw(WR) = 10 x n f(BCLK) X 2 10 x m f(BCLK)
9 9
- 15
[ns] (if external bus cycle is a + b, n=(b x 2)-1)
td(DB - WR) =
- 20
[ns]
(if external bus cycle is a + b, m=b)
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M32C/80 Group
5. Electrical Characteristics
VCC1=VCC2=3.3V
Switching Characteristics (VCC1 = VCC2 = 3.0 to 3.6V, VSS = 0V at Topr = -20 to 85oC unless otherwise specified) Table 5.38 Memory Expansion Mode and Microprocessor Mode (when accessing an external memory space with the multiplexed bus)
Symbol td(BCLK-AD) th(BCLK-AD) th(RD-AD) th(WR-AD) td(BCLK-CS) th(BCLK-CS) th(RD-CS) th(WR-CS) td(BCLK-RD) th(BCLK-RD) td(BCLK-WR) th(BCLK-WR) td(DB-WR) th(WR-DB) td(BCLK-ALE) th(BCLK-ALE) td(AD-ALE) th(ALE-AD) tdz(RD-AD) Parameter Address Output Delay Time Address Output Hold Time (BCLK standard) Address Output Hold Time (RD standard) Address Output Hold Time (WR standard) Chip-Select Signal Output Delay Time Chip-Select Signal Output Hold Time (BCLK standard) Chip-Select Signal Output Hold Time (RD standard) Chip-Select Signal Output Hold Time (WR standard) RD Signal Output Delay Time RD Signal Output Hold Time WR Signal Output Delay Time WR Signal Output Hold Time Data Output delay Time (WR standard) Data Output Hold Time (WR standard) ALE Signal Output Delay Time (BCLK standard) ALE Signal Output Hold Time (BCLK standard) ALE Signal Output Delay Time (address standard) ALE Signal Output Hold Time (address standard) Address Output Float Start Time -2 (Note 3) (Note 4) 8 0 (Note 2) (Note 1) 18 0 (Note 1) (Note 1) 0 (Note 1) (Note 1) 18 Measurement Condition Standard Min. Max. 18 ns ns ns ns ns ns ns ns 18 -3 18 ns ns ns ns ns ns ns ns ns ns ns Unit
See Figure 5.1
NOTES: 1. Values can be obtained by the following equations, according to BLCK frequency. th(RD - AD) = th(WR - AD) = th(RD - CS) = th(WR - CS) = th(WR - DB) = 10 9 f(BCLK) X 2 10 9 f(BCLK) X 2 10 9 f(BCLK) X 2 10 9 f(BCLK) X 2 10 9 f(BCLK) X 2 - 10 - 10 -10 - 10 - 20 [ns] [ns] [ns] [ns] [ns]
2. Values can be obtained by the following equations, according to BLCK frequency and external bus cycles. td(DB - WR) = 10 X m - 25 f(BCLK) X 2
9
[ns] (if external bus cycle is a + b, m=(b+2)-1)
3. Values can be obtained by the following equations, according to BLCK frequency and external bus cycles. td(AD - ALE) = 10 x n f(BCLK) X 2
9
- 20
[ns] (if external bus cycle is a + b, n=a)
4. Values can be obtained by the following equations, according to BLCK frequency and external bus cycles. th(ALE - AD) = 10 x n f(BCLK) X 2
9
- 10
[ns] (if external bus cycle is a + b, n=a)
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5. Electrical Characteristics
Vcc1=Vcc2=3.3V
Memory Expansion Mode and Microprocessor Mode
(when accessing an external memory space)
[Read Timing] (1 + 1 Bus Cycles)
BCLK
td(BCLK-CS)
18ns.max(1)
th(BCLK-CS)
0ns.min
CSi
tcyc
th(RD-CS)
0ns.min
td(BCLK-AD)
ADi BHE
18ns.max(1)
th(BCLK-AD)
0ns.min
td(BCLK-RD)
18ns.max
th(RD-AD)
0ns.min
RD
tac1(RD-DB)(2) tac1(AD-DB)(2)
DB
Hi-Z
th(BCLK-RD)
-3ns.min
tsu(DB-BCLK)
30ns.min(1)
th(RD-DB)
0ns.min
NOTES: 1. Values guaranteed only when the microcomputer is used independently. A maximum of 35ns is guaranteed for td(BCLK-AD)+tsu(DB-BCLK). 2. Varies with operation frequency. tac1(RD-DB)=(tcyc/2 x m-35)ns.max (if external bus cycle is a + b, m=(b x 2) + 1) tac1(AD-DB)=(tcyc x n-35)ns.max (if external bus cycle is a + b, n = a + b)
[Write Timing] (1 + 1 Bus Cycles)
BCLK
td(BCLK-CS)
18ns.max
th(BCLK-CS)
0ns.min
CSi
tcyc
th(WR-CS)(3) th(BCLK-AD)
0ns.min
td(BCLK-AD)
ADi BHE
18ns.max
td(BCLK-WR) tw(WR)(3)
18ns.max
th(WR-AD)(3) th(BCLK-WR)
0ns.min
WR,WRL, WRH
td(DB-WR)(3)
DBi
th(WR-DB)(3)
NOTE: 3. Varies with operation frequency. td(DB-WR)=(tcyc x m-20)ns.min (if external bus cycle is a + b, m=b) th(WR-DB)=(tcyc/2-20)ns.min th(WR-AD)=(tcyc/2-10)ns.min th(WR-CS)=(tcyc/2-10)ns.min tw(WR)=(tcyc/2 x n-15)ns.min (if external bus cycle is a + b, n=(bx2)-1)
Measurement Conditions * VCC1=VCC2=3.0 to 3.6V * Input high and low voltage: VIH=1.5V, VIL=0.5V * Output high and low voltage: VOH=1.5V, VOL=1.5V tcyc= 10 f(BCLK)
9
Figure 5.6 VCC1=VCC2=3.3V Timing Diagram (1)
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M32C/80 Group
5. Electrical Characteristics
Memory Expansion Mode and Microprocessor Mode
(when accessing external memory space and using the multiplexed bus)
Vcc1=Vcc2=3.3V
[ Read Timing ] (2 +2 Bus Cycles)
BCLK
td(BCLK-ALE)
18ns.max
th(BCLK-ALE)
-2ns.min
ALE
td(BCLK-CS)
18ns.max
tcyc
th(BCLK-CS)
0ns.min
CSi
th(RD-CS)(1) td(AD-ALE)(1) th(ALE-AD)
Address
(1)
tsu(DB-BCLK) 30ns.min tdz(RD-AD)
8ns.max
ADi /DBi
Data input
Address
td(BCLK-AD)
ADi BHE
18ns.max
tac2(RD-DB)(1)
(1)
th(RD-DB)
0ns.min
th(BCLK-AD)
0ns.min
tac2(AD-DB)
RD
td(BCLK-RD)
18ns.max
th(BCLK-RD)
-3ns.min
th(RD-AD)
(1)
NOTE: 1. Varies with operation frequency: td(AD-ALE)=(tcyc/2 x n-20)ns.min (if external bus cycle is a + b, n=a) th(ALE-AD)=(tcyc/2 x n-10)ns.min (if external bus cycle is a + b, n=a) th(RD-AD)=(tcyc/2-10)ns.min, th(RD-CS)=(tcyc/2-10)ns.min tac2(RD-DB)=(tcyc/2 x m-35)ns.max (if external bus cycle is a + b, m=(b x 2)-1) tac2(AD-DB)=(tcyc/2 x p-35)ns.max (if external bus cycle is a + b, p={(a+b-1) x 2}+1)
[ Write Timing ] (2 +2 Bus Cycles)
BCLK
td(BCLK-ALE)
18ns.max
th(BCLK-ALE)
-2ns.min
ALE
td(BCLK-CS)
18ns.max
tcyc
th(WR-CS)
(2)
th(BCLK-CS)
0ns.min
CSi
td(AD-ALE)
ADi /DBi
(2)
th(ALE-AD)
Address
(2)
Data output
Address
td(BCLK-AD)
ADi BHE
18ns.max
td(DB-WR)
(2)
th(WR-DB)
(2)
th(BCLK-AD)
0ns.min
td(BCLK-WR)
WR,WRL, WRH NOTE: 2. Varies with operation frequency: td(AD-ALE)=(tcyc/2 x n - 20)ns.min (if external bus cycle is a + b, n=a) th(ALE-AD)=(tcyc/2 x n -10)ns.min (if external bus cycle is a + b, n=a) th(WR-AD)=(tcyc/2-10)ns.min, th(WR-CS)=(tcyc/2-10)ns.min, th(WR-DB)=(tcyc/2-20)ns.min td(DB-WR)=(tcyc/2 x m-25)ns.min (if external bus cycle is a + b, m=(b x 2)-1)
18ns.max
th(BCLK-WR)
0ns.min
th(WR-AD) (2)
Measurement Conditions: * VCC1=VCC2=3.0 to 3.6V * Input high and low voltage: VIH=1.5V, VIL=0.5V * Output high and low voltage: VOH=1.5V, VOL=1.5V 9 tcyc= 10 f(BCLK)
Figure 5.7 VCC1=VCC2=3.3V Timing Diagram (2)
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5. Electrical Characteristics
Vcc1=Vcc2=3.3V tc(TA) tw(TAH) TAiIN Input tw(TAL) tc(UP) tw(UPH) TAiOUT Input tw(UPL) TAiOUT Input (Counter increment/ decrement input) In event counter mode TAiIN Input
(When counting on falling edge)
th(TIN-UP)
tsu(UP-TIN)
TAiIN Input
(When counting on rising edge)
tc(TB) tw(TBH) TBiIN Input tw(TBL) tc(AD) tw(ADL) ADTRG Input tc(CK) tw(CKH) CLKi tw(CKL) TxDi td(C-Q) RxDi tw(INL) INTi Input tw(INH) tsu(D-C) th(C-D) th(C-Q)
NMI input
2 CPU clock cycles + 300ns or more ("L" width) 2 CPU clock cycles + 300ns or more
Figure 5.8 VCC1=VCC2=3.3V Timing Diagram (3)
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M32C/80 Group
5. Electrical Characteristics
Vcc1=Vcc2=3.3V
Memory Expansion Mode and Microprocessor Mode
BCLK RD (Separate bus) WR, WRL, WRH (Separate bus) RD (Multiplexed bus) WR, WRL, WRH (Multiplexed bus) RDY input tsu(RDY-BCLK) th(BCLK-RDY)
BCLK tsu(HOLD-BCLK) HOLD input th(BCLK-HOLD)
HLDA output P0, P1, P2, P3, P4, P50 to P52 td(BCLK-HLDA) td(BCLK-HLDA)
Hi-Z
Measurement Conditions: * VCC1=VCC2=3.0 to 3.6V * Input high and low voltage: VIH=2.4V, VIL=0.6V * Output high and low voltage: VOH=1.5V, VOL=1.5V
Figure 5.9 VCC1=VCC2=3.3V Timing Diagram (4)
Rev. 1.10 Nov. 01, 2005 Page 55 REJ03B0038-0110
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M32C/80 Group
Package Dimensions
Package Dimensions
JEITA Package Code P-LQFP100-14x14-0.50 RENESAS Code PLQP0100KB-A Previous Code 100P6Q-A / FP-100U / FP-100UV MASS[Typ.] 0.6g
HD *1 D
75
51 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET.
76
50
bp b1
HE E
Reference Symbol
*2
Dimension in Millimeters
c1
c
Terminal cross section
1 Index mark ZD
25 F
ZE
100
26
A2
A
D E A2 HD HE A A1 bp b1 c c1
c
A1
y e
*3
bp
L L1 Detail F
x
e x y ZD ZE L L1
Min Nom Max 13.9 14.0 14.1 13.9 14.0 14.1 1.4 15.8 16.0 16.2 15.8 16.0 16.2 1.7 0.05 0.1 0.15 0.15 0.20 0.25 0.18 0.09 0.145 0.20 0.125 0 8 0.5 0.08 0.08 1.0 1.0 0.35 0.5 0.65 1.0
JEITA Package Code P-QFP100-14x20-0.65
RENESAS Code PRQP0100JB-A
Previous Code 100P6S-A
MASS[Typ.] 1.6g
HD *1 80
D 51
81
50 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET.
*2
HE
E
ZE
Reference Symbol
Dimension in Millimeters
100
31
1
ZD
Index mark
30 F
c
L e y *3 bp Detail F
D E A2 HD HE A A1 bp c e y ZD ZE L
Min Nom Max 19.8 20.0 20.2 13.8 14.0 14.2 2.8 22.5 22.8 23.1 16.5 16.8 17.1 3.05 0.1 0.2 0 0.25 0.3 0.4 0.13 0.15 0.2 0 10 0.5 0.65 0.8 0.10 0.575 0.825 0.4 0.6 0.8
A
Rev. 1.10 Nov. 01, 2005 Page 56 REJ03B0038-0110
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A1
A2
REVISION HISTORY
Rev. 0.10 0.11 0.12 Date Page Sep., 02 Sep., 02 Nov., 02 - 3 3 New Document Table 1.1.1 "CAN" deleted
M32C/80 Group Datasheet
Description Summary
Table 1.1.1 "4.2 to 5.5V" --> "3.0 to 5.5V" "3.0 to 3.6V (f(XIN)=20MHz without software wait)" deleted "26mA (f(XIN)=20MHz without software wait,Vcc=3.3V)" deleted 1. Overview 1.2 Performance Outline 1.3 Block Diagram 1.5 Pin Assignments Table 1.3 Pin Characteristics for 100-Pin Package 1.6 Pin Description 2. Central Processing Unit (CPU) 3. Memory 4. Special Function Registers (SFR) changed changed added changed changed added added added added
0.30
Aug., 02
-
0.40 1.00
Jun., 04 Nov., 04
All pages Words standardized: On-chip oscillator, A/D converter and D/A converter Overview 2, 3 * Table 1.1 and 1.2 M32C/80 Group Performance "When using 16-bit bus" added to I/O ports "Option" deleted from Serial I/O, I2C bus, and IEBus "Voltage Detection Circuit" added Value added to "Power Consumption" "Flash Memory" added 4 * 1.3 Block Diagram Description deleted 5 * Figure 1.2 ROM/RAM Capacity deleted * Table 1.3 M32C/85 Group Note1 deleted 11 * Table 1.5 Pin Description Note 1 added to I/O ports Memory 23 * Chapter Description modified * Figure 3.1 Memory Map modified SFR 16* "X: Nothing is assigned" modified to "X: Indeterminate" * "?: Indeterminate" modified to "X: Indeterminate" * "Users cannot use any symbols with *" deleted * Register names, symbols, value after RESET of addresses 001716, 001B16, 001F16, 002B16, 002F16, 004C16, and 004D16 deleted * Value after RESET in the PM0 register revised 16 * Note 3 deleted 29 * Note 1 added to addresses 03E016 to 03EB16
A-1
REVISION HISTORY
Rev. Date Page 30All pages 1 2 3 9
M32C/80 Group Datasheet
Description Summary
1.10
Nov., 05
Electrical Characteristics * This capter added Package code chnaged: 100P6Q-A to PLQP0100KB-A and 100P6S-A to PRQP0100JB-A Overview * Note that the M32C/80 Group is ROMless device added * Table 1.1 M32C/80 Group Performance Item "HDLC Data Processing" changed to "Intelligent I/O Communication Function"; item "Flash Memory" deleted * Figure 1.1 M32C/80 Group Block Diagram Notes 1 and 2 added * Table 1.4 Pin Description Supply voltage for analog power supply input modi______
15 16 17 19 20 21 26 27, 28 28 3032 33 34 35 41 42 46 47 52
fied "-" to "VCC1"; description for CNVSS changed; supply voltage for INT interrupt input modified; note for I/O ports added Memory * Figure 3.1 Memory Map Disgram changed; note added Special Function Registers (SFRs) * Note 2 deleted * Values after RESET in the RMAD6 and RMAD7 registers modified * Value after RESET in the RLVL register modified * Value after RESET in the G0RB register modified * Values after RESET in the G0EMR, G0ERC, and G0IRF registers modified * Value after RESET in the TCSPR register modified; note 1 added * Register names, symbols, and value after RESET of addresses 039216 and 03AC16 deleted * Value after RESET in the PSC register modified Electrical Characteristics * Ports P11 to P15 deleted * Table 5.2 Recpmmended Operating Conditions f(BCLK) standard added * Table 5.3 Electrical Characteristics Max. standard for ICC modified * Table 5.4 A/D Conversion Characteristics AN00 to AN07 deleted from "INL" row * Table 5.7 Memory Expansion Mode and Microprocessor Mode Expressions on note 1 corrected * Figure 5.2 VCC1=VCC2=5V Timing Diagram (1) Expression for tcyc added; note 3 corrected * Figure 5.3 VCC1=VCC2=5V Timing Diagram (2) Expression for tcyc added; notes 1 and 2 corrected * Table 5.22 A/D Conversion Characteristics Min. standard for VREF modified * Table 5.25 Memory Expansion Mode and Microprocessor Mode Expressions on note 1 corrected * Figure 5.6 VCC1=VCC2=3.3V Timing Diagram (1) Expression for tcyc added; note 3 corrected A-2
REVISION HISTORY
Rev. Date Page 53
M32C/80 Group Datasheet
Description Summary
* Figure 5.7 VCC1=VCC2=3.3V Timing Diagram (2) Expression for tcyc added; notes 1 and 2 corrected
A-3
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